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Searched refs:RING_HWSTAM (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/i915/gvt/
A Dmmio_context.c84 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
138 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
A Dhandlers.c2215 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL); in init_generic_mmio_info()
/drivers/gpu/drm/xe/regs/
A Dxe_engine_regs.h78 #define RING_HWSTAM(base) XE_REG((base) + 0x98) macro
/drivers/gpu/drm/i915/gt/
A Dintel_engine_regs.h72 #define RING_HWSTAM(base) _MMIO((base) + 0x98) macro
A Dintel_engine_cs.c380 ENGINE_WRITE(engine, RING_HWSTAM, mask); in intel_engine_set_hwsp_writemask()
382 ENGINE_WRITE16(engine, RING_HWSTAM, mask); in intel_engine_set_hwsp_writemask()
/drivers/gpu/drm/xe/
A Dxe_hw_engine.c337 xe_hw_engine_mmio_write32(hwe, RING_HWSTAM(0), ~0x0); in xe_hw_engine_enable_ring()
A Dxe_wa.c458 XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0))
A Dxe_guc_capture.c111 { RING_HWSTAM(0), REG_32BIT, 0, 0, 0, "HWSTAM"}, \
/drivers/gpu/drm/i915/
A Dintel_gvt_mmio_table.c71 MMIO_RING_D(RING_HWSTAM); in iterate_generic_mmio()

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