Searched refs:RING_IMR (Results 1 – 11 of 11) sorted by relevance
| /drivers/gpu/drm/i915/gt/ |
| A D | gen6_engine_cs.c | 427 ENGINE_WRITE(engine, RING_IMR, in gen6_irq_enable()
431 ENGINE_POSTING_READ(engine, RING_IMR); in gen6_irq_enable()
438 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); in gen6_irq_disable()
444 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask); in hsw_irq_enable_vecs()
447 ENGINE_POSTING_READ(engine, RING_IMR); in hsw_irq_enable_vecs()
454 ENGINE_WRITE(engine, RING_IMR, ~0); in hsw_irq_disable_vecs()
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| A D | intel_engine_regs.h | 80 #define RING_IMR(base) _MMIO((base) + 0xa8) macro
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| A D | intel_execlists_submission.c | 3252 ENGINE_WRITE(engine, RING_IMR, in gen8_logical_ring_enable_irq()
3254 ENGINE_POSTING_READ(engine, RING_IMR); in gen8_logical_ring_enable_irq()
3259 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); in gen8_logical_ring_disable_irq()
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| A D | intel_engine_cs.c | 2108 ENGINE_READ(engine, RING_IMR)); in intel_engine_print_registers()
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| /drivers/gpu/drm/xe/regs/ |
| A D | xe_engine_regs.h | 86 #define RING_IMR(base) XE_REG((base) + 0xa8) macro
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| /drivers/gpu/drm/xe/ |
| A D | xe_guc_ads.c | 768 { .reg = RING_IMR(hwe->mmio_base), }, in guc_mmio_regset_write()
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| A D | xe_guc_capture.c | 121 { RING_IMR(0), REG_32BIT, 0, 0, 0, "RING_IMR"}, \
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| A D | xe_lrc.c | 629 regs[CTX_INT_MASK_ENABLE_REG] = RING_IMR(0).addr; in set_memory_based_intr()
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| /drivers/gpu/drm/i915/gt/uc/ |
| A D | intel_guc_ads.c | 393 ret |= GUC_MMIO_REG_ADD(gt, regset, RING_IMR(base), false); in guc_mmio_regset_init()
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| /drivers/gpu/drm/i915/ |
| A D | intel_gvt_mmio_table.c | 66 MMIO_RING_D(RING_IMR); in iterate_generic_mmio()
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| /drivers/gpu/drm/i915/gvt/ |
| A D | handlers.c | 2208 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, in init_generic_mmio_info()
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