Home
last modified time | relevance | path

Searched refs:RING_START (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/i915/gt/
A Dintel_ring_submission.c225 ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma)); in xcs_resume()
298 ENGINE_READ(engine, RING_START), in xcs_resume()
367 ENGINE_READ_FW(engine, RING_START)); in reset_prepare()
382 ENGINE_READ_FW(engine, RING_START)); in reset_prepare()
A Dintel_engine_regs.h19 #define RING_START(base) _MMIO((base) + 0x38) macro
A Dselftest_lrc.c305 i915_mmio_reg_offset(RING_START(engine->mmio_base)), in live_lrc_fixed()
445 *cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base)); in __live_lrc_state()
1597 *cs++ = i915_mmio_reg_offset(RING_START(0)); in emit_wabb_ctx_canary()
A Dintel_gt.c149 intel_uncore_write(uncore, RING_START(base), 0); in init_unused_ring()
A Dintel_engine_cs.c2092 ENGINE_READ(engine, RING_START)); in intel_engine_print_registers()
A Dintel_execlists_submission.c1967 ENGINE_READ(engine, RING_START), in process_csb()
/drivers/gpu/drm/xe/regs/
A Dxe_engine_regs.h56 #define RING_START(base) XE_REG((base) + 0x38) macro
/drivers/gpu/drm/i915/
A Di915_request.c2239 u32 ring = ENGINE_READ(engine, RING_START); in engine_match_ring()
A Dintel_gvt_mmio_table.c95 MMIO_RING_D(RING_START); in iterate_generic_mmio()
A Di915_gpu_error.c1279 ee->start = ENGINE_READ(engine, RING_START); in engine_record_registers()
/drivers/gpu/drm/i915/gt/uc/
A Dintel_guc_capture.c67 { RING_START(0), 0, 0, "START" }, \
/drivers/gpu/drm/xe/
A Dxe_guc_capture.c129 { RING_START(0), REG_64BIT_LOW_DW, 0, 0, 0, NULL}, \
/drivers/gpu/drm/i915/gvt/
A Dscheduler.c653 vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) = in update_vreg_in_ctx()
A Dhandlers.c2246 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); in init_generic_mmio_info()

Completed in 48 milliseconds