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Searched refs:RISCV_IOMMU_CMD_OPCODE (Results 1 – 1 of 1) sorted by relevance

/drivers/iommu/riscv/
A Diommu-bits.h462 #define RISCV_IOMMU_CMD_OPCODE GENMASK_ULL(6, 0) macro
713 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOTINVAL_OPCODE) | in riscv_iommu_cmd_inval_vma()
741 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOFENCE_OPCODE) | in riscv_iommu_cmd_iofence()
750 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOFENCE_OPCODE) | in riscv_iommu_cmd_iofence_set_av()
759 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IODIR_OPCODE) | in riscv_iommu_cmd_iodir_inval_ddt()
766 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IODIR_OPCODE) | in riscv_iommu_cmd_iodir_inval_pdt()

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