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Searched refs:RISCV_IOMMU_DDTP_IOMMU_MODE (Results 1 – 2 of 2) sorted by relevance

/drivers/iommu/riscv/
A Diommu.c656 FIELD_PREP(RISCV_IOMMU_DDTP_IOMMU_MODE, in riscv_iommu_disable()
683 mode = FIELD_GET(RISCV_IOMMU_DDTP_IOMMU_MODE, ddtp); in riscv_iommu_iodir_alloc()
688 FIELD_PREP(RISCV_IOMMU_DDTP_IOMMU_MODE, mode)); in riscv_iommu_iodir_alloc()
730 mode = FIELD_GET(RISCV_IOMMU_DDTP_IOMMU_MODE, ddtp); in riscv_iommu_iodir_set_mode()
738 rq_ddtp = FIELD_PREP(RISCV_IOMMU_DDTP_IOMMU_MODE, rq_mode); in riscv_iommu_iodir_set_mode()
751 mode = FIELD_GET(RISCV_IOMMU_DDTP_IOMMU_MODE, ddtp); in riscv_iommu_iodir_set_mode()
1559 if (FIELD_GET(RISCV_IOMMU_DDTP_IOMMU_MODE, ddtp) > in riscv_iommu_init_check()
A Diommu-bits.h88 #define RISCV_IOMMU_DDTP_IOMMU_MODE GENMASK_ULL(3, 0) macro

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