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Searched refs:RREG32_SOC15 (Results 1 – 25 of 139) sorted by relevance

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/drivers/gpu/drm/amd/amdgpu/
A Dnbio_v4_3.c246 def = data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL); in nbio_v4_3_update_medium_grain_clock_gating()
276 def = data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2); in nbio_v4_3_update_medium_grain_light_sleep()
293 data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL); in nbio_v4_3_get_clockgating_state()
298 data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2); in nbio_v4_3_get_clockgating_state()
353 data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL); in nbio_v4_3_get_rom_offset()
395 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL); in nbio_v4_3_program_aspm()
402 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7); in nbio_v4_3_program_aspm()
407 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3); in nbio_v4_3_program_aspm()
437 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4); in nbio_v4_3_program_aspm()
460 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL); in nbio_v4_3_program_aspm()
[all …]
A Dnbif_v6_3_1.c43 u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); in nbif_v6_3_1_get_rev_id()
63 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); in nbif_v6_3_1_get_memsize()
299 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2); in nbif_v6_3_1_init_registers()
308 data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL); in nbif_v6_3_1_get_rom_offset()
350 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL); in nbif_v6_3_1_program_aspm()
357 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7); in nbif_v6_3_1_program_aspm()
362 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3); in nbif_v6_3_1_program_aspm()
392 def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2); in nbif_v6_3_1_program_aspm()
399 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4); in nbif_v6_3_1_program_aspm()
422 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL); in nbif_v6_3_1_program_aspm()
[all …]
A Dgfxhub_v2_1.c110 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_1_get_fb_location()
120 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_1_get_mc_fb_offset()
195 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_init_tlb_regs()
220 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_1_init_cache_regs()
233 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_1_init_cache_regs()
264 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); in gfxhub_v2_1_enable_system_domain()
397 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_gart_disable()
428 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_1_set_fault_enable_default()
564 adev->gmc.VM_DEBUG = RREG32_SOC15(GC, 0, mmGCVM_DEBUG); in gfxhub_v2_1_save_regs()
642 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); in gfxhub_v2_1_halt()
[all …]
A Dimu_v12_0.c130 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); in imu_v12_0_wait_for_reset_status()
152 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16); in imu_v12_0_setup()
156 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10); in imu_v12_0_setup()
167 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL); in imu_v12_0_start()
311 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_TOP); in imu_v12_init_gfxhub_settings()
313 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET); in imu_v12_init_gfxhub_settings()
315 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE); in imu_v12_init_gfxhub_settings()
317 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT); in imu_v12_init_gfxhub_settings()
319 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP); in imu_v12_init_gfxhub_settings()
321 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in imu_v12_init_gfxhub_settings()
[all …]
A Dnbio_v7_7.c42 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); in nbio_v7_7_get_rev_id()
61 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE); in nbio_v7_7_get_memsize()
148 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, in nbio_v7_7_ih_doorbell_range()
176 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL); in nbio_v7_7_ih_control()
240 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3); in nbio_v7_7_init_registers()
251 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23); in nbio_v7_7_init_registers()
265 def = data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL); in nbio_v7_7_update_medium_grain_clock_gating()
294 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2); in nbio_v7_7_update_medium_grain_light_sleep()
303 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1); in nbio_v7_7_update_medium_grain_light_sleep()
322 data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL); in nbio_v7_7_get_clockgating_state()
[all …]
A Dnbio_v7_11.c42 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0); in nbio_v7_11_get_rev_id()
61 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE); in nbio_v7_11_get_memsize()
142 reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN); in nbio_v7_11_enable_doorbell_aperture()
177 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,regGDC0_BIF_IH_DOORBELL_RANGE); in nbio_v7_11_ih_doorbell_range()
204 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL); in nbio_v7_11_ih_control()
268 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3); in nbio_v7_11_init_registers()
282 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23); in nbio_v7_11_init_registers()
296 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL); in nbio_v7_11_update_medium_grain_clock_gating()
325 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2); in nbio_v7_11_update_medium_grain_light_sleep()
353 data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL); in nbio_v7_11_get_clockgating_state()
[all …]
A Dumsch_mm_v4_0.c76 data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL); in umsch_mm_v4_0_load_microcode()
129 data = RREG32_SOC15(VCN, 0, regUVD_UMSCH_FORCE); in umsch_mm_v4_0_load_microcode()
134 data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL); in umsch_mm_v4_0_load_microcode()
154 data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL); in umsch_mm_v4_0_load_microcode()
167 RREG32_SOC15(VCN, 0, regVCN_MES_MSTATUS_LO)); in umsch_mm_v4_0_load_microcode()
189 data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL0); in umsch_mm_v4_0_aggregated_doorbell_init()
195 data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL1); in umsch_mm_v4_0_aggregated_doorbell_init()
201 data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL2); in umsch_mm_v4_0_aggregated_doorbell_init()
207 data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL3); in umsch_mm_v4_0_aggregated_doorbell_init()
235 data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE); in umsch_mm_v4_0_ring_start()
[all …]
A Dsmuio_v13_0.c48 def = data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); in smuio_v13_0_update_rom_clock_gating()
69 data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); in smuio_v13_0_get_clock_gating_state()
85 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_die_id()
102 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_socket_id()
119 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_is_host_gpu_xgmi_supported()
136 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_pkg_type()
A Dmmhub_v2_3.c190 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_init_tlb_regs()
209 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_3_init_cache_regs()
222 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); in mmhub_v2_3_init_cache_regs()
253 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); in mmhub_v2_3_enable_system_domain()
386 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_gart_disable()
393 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_3_gart_disable()
498 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); in mmhub_v2_3_update_medium_grain_clock_gating()
590 data = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); in mmhub_v2_3_get_clockgating()
591 data1 = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL); in mmhub_v2_3_get_clockgating()
592 data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL); in mmhub_v2_3_get_clockgating()
[all …]
A Dvcn_v4_0_5.c345 RREG32_SOC15(VCN, i, regUVD_STATUS))) { in vcn_v4_0_5_hw_fini()
1095 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); in vcn_v4_0_5_start()
1101 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); in vcn_v4_0_5_start()
1109 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); in vcn_v4_0_5_start()
1208 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_5_start()
1215 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); in vcn_v4_0_5_start()
1219 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_5_start()
1226 RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_5_start()
1262 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS); in vcn_v4_0_5_stop_dpg_mode()
1306 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); in vcn_v4_0_5_stop()
[all …]
A Dsmu_v11_0_i2c.c51 uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT); in smu_v11_0_i2c_set_clock_gating()
87 u32 en_stat = RREG32_SOC15(SMUIO, in smu_v11_0_i2c_enable()
108 RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR); in smu_v11_0_i2c_clear_status()
187 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_poll_tx_status()
195 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT); in smu_v11_0_i2c_poll_tx_status()
249 reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_poll_rx_status()
298 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_transmit()
422 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD); in smu_v11_0_i2c_receive()
468 reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE); in smu_v11_0_i2c_activity_done()
529 status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_fini()
[all …]
A Dvcn_v1_0.c286 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) { in vcn_v1_0_hw_fini()
518 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
528 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
551 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
864 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); in vcn_v1_0_start_spg_mode()
877 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); in vcn_v1_0_start_spg_mode()
1015 RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v1_0_start_spg_mode()
1165 RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v1_0_start_dpg_mode()
1233 RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v1_0_stop_spg_mode()
1249 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); in vcn_v1_0_stop_dpg_mode()
[all …]
A Dmmhub_v2_0.c260 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_init_tlb_regs()
285 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_0_init_cache_regs()
298 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); in mmhub_v2_0_init_cache_regs()
329 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); in mmhub_v2_0_enable_system_domain()
454 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_gart_disable()
461 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_0_gart_disable()
578 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); in mmhub_v2_0_update_medium_grain_clock_gating()
579 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); in mmhub_v2_0_update_medium_grain_clock_gating()
635 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); in mmhub_v2_0_update_medium_grain_light_sleep()
690 data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); in mmhub_v2_0_get_clockgating()
[all …]
A Dmmhub_v3_0.c215 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_init_tlb_regs()
241 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_init_cache_regs()
254 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v3_0_init_cache_regs()
285 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v3_0_enable_system_domain()
410 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_gart_disable()
417 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_gart_disable()
529 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in mmhub_v3_0_get_fb_location()
552 def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2); in mmhub_v3_0_update_medium_grain_clock_gating()
553 def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2); in mmhub_v3_0_update_medium_grain_clock_gating()
608 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); in mmhub_v3_0_update_medium_grain_light_sleep()
[all …]
A Dmmhub_v3_3.c314 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_3_init_tlb_regs()
334 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_3_init_cache_regs()
347 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v3_3_init_cache_regs()
378 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v3_3_enable_system_domain()
501 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4); in mmhub_v3_3_init_saw_regs()
547 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_3_gart_disable()
554 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_3_gart_disable()
666 offset = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET); in mmhub_v3_3_get_mc_fb_offset()
678 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); in mmhub_v3_3_update_medium_grain_clock_gating()
694 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); in mmhub_v3_3_update_medium_grain_light_sleep()
[all …]
A Dmmhub_v4_1_0.c208 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_1_0_init_tlb_regs()
234 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v4_1_0_init_cache_regs()
247 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v4_1_0_init_cache_regs()
278 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v4_1_0_enable_system_domain()
403 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v4_1_0_gart_disable()
410 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v4_1_0_gart_disable()
523 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in mmhub_v4_1_0_get_fb_location()
547 def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2); in mmhub_v4_1_0_update_medium_grain_clock_gating()
548 def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2); in mmhub_v4_1_0_update_medium_grain_clock_gating()
588 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); in mmhub_v4_1_0_update_medium_grain_light_sleep()
[all …]
A Dmmhub_v1_0.c40 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP); in mmhub_v1_0_get_fb_location()
142 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_init_tlb_regs()
165 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); in mmhub_v1_0_init_cache_regs()
176 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); in mmhub_v1_0_init_cache_regs()
203 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); in mmhub_v1_0_enable_system_domain()
272 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CNTL4); in mmhub_v1_0_init_saw()
402 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_gart_disable()
412 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); in mmhub_v1_0_gart_disable()
566 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); in mmhub_v1_0_update_medium_grain_light_sleep()
608 data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); in mmhub_v1_0_get_clockgating()
[all …]
A Ddf_v1_7.c49 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); in df_v1_7_enable_broadcast_mode()
61 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); in df_v1_7_get_fb_channel_number()
88 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
93 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
109 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_get_clockgating_state()
A Dvcn_v5_0_1.c684 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_1_start_dpg_mode()
691 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR); in vcn_v5_0_1_start_dpg_mode()
695 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_1_start_dpg_mode()
705 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); in vcn_v5_0_1_start_dpg_mode()
944 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); in vcn_v5_0_1_start()
1023 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); in vcn_v5_0_1_start()
1036 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR); in vcn_v5_0_1_start()
1048 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); in vcn_v5_0_1_start()
1078 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); in vcn_v5_0_1_stop_dpg_mode()
1088 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); in vcn_v5_0_1_stop_dpg_mode()
[all …]
A Dsmuio_v14_0_2.c45 clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); in smuio_v14_0_2_get_gpu_clock_counter()
46 clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); in smuio_v14_0_2_get_gpu_clock_counter()
48 clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); in smuio_v14_0_2_get_gpu_clock_counter()
50 clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); in smuio_v14_0_2_get_gpu_clock_counter()
A Dvcn_v5_0_0.c312 RREG32_SOC15(VCN, i, regUVD_STATUS))) { in vcn_v5_0_0_hw_fini()
801 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS); in vcn_v5_0_0_start_dpg_mode()
852 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); in vcn_v5_0_0_start()
858 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); in vcn_v5_0_0_start()
939 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v5_0_0_start()
946 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); in vcn_v5_0_0_start()
950 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v5_0_0_start()
958 RREG32_SOC15(VCN, i, regUVD_STATUS); in vcn_v5_0_0_start()
994 RREG32_SOC15(VCN, inst_idx, regUVD_STATUS); in vcn_v5_0_0_stop_dpg_mode()
1040 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); in vcn_v5_0_0_stop()
[all …]
A Dgfx_v11_0.c978 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
2121 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); in gfx_v11_0_constants_init()
2673 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2796 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_me_cache_rs64()
2957 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
2979 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
3034 bootload_status = RREG32_SOC15(GC, 0, in gfx_v11_0_wait_for_rlc_autoload_complete()
3107 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) in gfx_v11_0_cp_gfx_enable()
5029 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
5030 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
[all …]
A Dhdp_v5_0.c53 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_mem_power_gating()
54 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_update_mem_power_gating()
144 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_medium_grain_clock_gating()
180 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_get_clockgating_state()
190 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_get_clockgating_state()
203 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); in hdp_v5_0_init_registers()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega10_thermal.c104 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), in vega10_fan_ctrl_get_fan_speed_rpm()
132 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
135 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
141 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
144 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
161 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
165 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
274 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), in vega10_fan_ctrl_set_fan_speed_pwm()
389 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); in vega10_thermal_set_temperature_range()
415 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), in vega10_thermal_initialize()
[all …]
A Dvega20_thermal.c95 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega20_fan_ctrl_set_static_mode()
98 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega20_fan_ctrl_set_static_mode()
124 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_get_fan_speed_pwm()
126 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), in vega20_fan_ctrl_get_fan_speed_pwm()
152 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_set_fan_speed_pwm()
163 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), in vega20_fan_ctrl_set_fan_speed_pwm()
206 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), in vega20_fan_ctrl_set_fan_speed_rpm()
223 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); in vega20_thermal_get_temperature()
260 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); in vega20_thermal_set_temperature_range()

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