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Searched refs:RREG32_SOC15_IP (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dsdma_v7_0.c459 mcu_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); in sdma_v7_0_enable()
572 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); in sdma_v7_0_gfx_resume_instance()
579 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); in sdma_v7_0_gfx_resume_instance()
585 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); in sdma_v7_0_gfx_resume_instance()
594 temp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); in sdma_v7_0_gfx_resume_instance()
718 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL)); in sdma_v7_0_load_microcode()
727 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL)); in sdma_v7_0_load_microcode()
733 ic_op_cntl = RREG32_SOC15_IP(GC, in sdma_v7_0_load_microcode()
735 sdma_status = RREG32_SOC15_IP(GC, in sdma_v7_0_load_microcode()
764 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL)); in sdma_v7_0_soft_reset()
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A Dsdma_v6_0.c400 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v6_0_gfx_stop()
466 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); in sdma_v6_0_enable()
498 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v6_0_gfx_resume_instance()
576 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); in sdma_v6_0_gfx_resume_instance()
583 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); in sdma_v6_0_gfx_resume_instance()
589 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); in sdma_v6_0_gfx_resume_instance()
599 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); in sdma_v6_0_gfx_resume_instance()
609 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); in sdma_v6_0_gfx_resume_instance()
768 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); in sdma_v6_0_soft_reset()
771 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); in sdma_v6_0_soft_reset()
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A Dsdma_v5_2.c419 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_gfx_stop()
422 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_2_gfx_stop()
555 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_gfx_resume_instance()
583 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, in sdma_v5_2_gfx_resume_instance()
613 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); in sdma_v5_2_gfx_resume_instance()
614 …doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSE… in sdma_v5_2_gfx_resume_instance()
648 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); in sdma_v5_2_gfx_resume_instance()
654 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); in sdma_v5_2_gfx_resume_instance()
672 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_2_gfx_resume_instance()
A Dsdma_v5_0.c355 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_0_ring_get_wptr()
357 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_0_ring_get_wptr()
569 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_stop()
572 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_0_gfx_stop()
706 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_resume_instance()
733 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, in sdma_v5_0_gfx_resume_instance()
767 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); in sdma_v5_0_gfx_resume_instance()
768 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, in sdma_v5_0_gfx_resume_instance()
825 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_0_gfx_resume_instance()
A Dsoc15_common.h70 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP, 0) macro
A Dgfx_v12_0.c1885 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_enable_gui_idle_interrupt()
4726 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_gfx_eop_interrupt_state()
4734 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_gfx_eop_interrupt_state()
4777 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v12_0_set_compute_eop_interrupt_state()
4785 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v12_0_set_compute_eop_interrupt_state()
4896 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_priv_reg_fault_state()
4910 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_priv_reg_fault_state()
4942 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_bad_op_fault_state()
4956 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_bad_op_fault_state()
4987 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_priv_inst_fault_state()
A Dgfx_v11_0.c2203 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_enable_gui_idle_interrupt()
6317 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_gfx_eop_interrupt_state()
6325 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_gfx_eop_interrupt_state()
6374 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
6382 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
6493 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_priv_reg_fault_state()
6507 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_priv_reg_fault_state()
6539 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_bad_op_fault_state()
6553 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_bad_op_fault_state()
6694 tmp = RREG32_SOC15_IP(GC, target);
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A Damdgpu_gmc.c958 RREG32_SOC15_IP(GC, reg) : in amdgpu_gmc_set_vm_fault_masks()
959 RREG32_SOC15_IP(MMHUB, reg); in amdgpu_gmc_set_vm_fault_masks()
A Damdgpu_amdkfd_gfx_v10_3.c338 (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \ in hqd_dump_v10_3()
A Dgmc_v9_0.c495 tmp = RREG32_SOC15_IP(MMHUB, reg); in gmc_v9_0_vm_fault_interrupt_state()
523 tmp = RREG32_SOC15_IP(MMHUB, reg); in gmc_v9_0_vm_fault_interrupt_state()
A Dgfx_v10_0.c5432 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_enable_gui_idle_interrupt()
9079 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state()
9085 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state()
9132 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
9138 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
9246 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_priv_reg_fault_state()
9260 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_priv_reg_fault_state()
9292 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_bad_op_fault_state()
9306 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_bad_op_fault_state()
9436 tmp = RREG32_SOC15_IP(GC, target); in gfx_v10_0_kiq_set_interrupt_state()
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A Damdgpu_amdkfd_gfx_v10.c352 (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \ in kgd_hqd_dump()
A Damdgpu_amdkfd_gfx_v9.c965 reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, GET_INST(GC, inst), in get_wave_count()
A Dsoc15.c487 RREG32_SOC15_IP(GC, reg) : RREG32(reg); in soc15_program_register_sequence()
A Dgfx_v9_0.c5986 mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
5992 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
6047 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v9_0_set_priv_reg_fault_state()
6083 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v9_0_set_bad_op_fault_state()

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