Searched refs:RVU_PF_VFFLR_INT_ENA_W1SX (Results 1 – 6 of 6) sorted by relevance
| /drivers/net/ethernet/marvell/octeontx2/af/cn20k/ |
| A D | mbox_init.c | 375 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); in cn20k_rvu_enable_afvf_intr()
387 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); in cn20k_rvu_enable_afvf_intr()
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| /drivers/crypto/marvell/octeontx2/ |
| A D | otx2_cptpf_main.c | 80 RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(num_vfs)); in cptpf_enable_vf_flr_me_intrs()
94 RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(num_vfs - 64)); in cptpf_enable_vf_flr_me_intrs()
171 RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); in cptpf_flr_wq_handler()
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| /drivers/net/ethernet/marvell/octeontx2/nic/ |
| A D | otx2_reg.h | 28 #define RVU_PF_VFFLR_INT_ENA_W1SX(a) (0x940 | (a) << 3) macro
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| A D | otx2_pf.c | 141 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); in otx2_flr_handler()
260 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); in otx2_register_flr_me_intr()
270 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), in otx2_register_flr_me_intr()
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| /drivers/net/ethernet/marvell/octeontx2/af/ |
| A D | rvu_reg.h | 94 #define RVU_PF_VFFLR_INT_ENA_W1SX(a) (0x940 | (a) << 3) macro
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| A D | rvu.c | 2815 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); in rvu_afvf_flr_handler()
3295 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); in rvu_enable_afvf_intr()
3307 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); in rvu_enable_afvf_intr()
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