Searched refs:SDMA1_REGISTER_OFFSET (Results 1 – 12 of 12) sorted by relevance
| /drivers/gpu/drm/radeon/ |
| A D | cik_sdma.c | 73 reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_get_rptr()
97 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_get_wptr()
118 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_set_wptr()
262 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_stop()
312 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
344 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_enable()
379 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_resume()
492 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_sdma_load_microcode()
495 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); in cik_sdma_load_microcode()
508 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_sdma_load_microcode()
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| A D | cik.c | 166 case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET): in cik_get_allowed_info_register()
4814 RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); in cik_print_gpu_status_regs()
4871 tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); in cik_gpu_check_soft_reset()
4960 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_soft_reset()
4962 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
5161 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
5163 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5515 WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
6170 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
6866 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
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| A D | cikd.h | 1953 #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ macro
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| /drivers/gpu/drm/amd/amdgpu/ |
| A D | cik_sdma.c | 50 SDMA1_REGISTER_OFFSET
880 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
890 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
908 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
918 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
1060 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_soft_reset()
1062 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset()
1112 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1114 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1117 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
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| A D | sdma_v2_4.c | 62 SDMA1_REGISTER_OFFSET
958 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_soft_reset()
960 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset()
1011 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1013 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1016 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1018 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
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| A D | sdma_v3_0.c | 77 SDMA1_REGISTER_OFFSET
1349 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1351 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1354 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1356 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
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| A D | amdgpu_amdkfd_gfx_v7.c | 140 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + in get_sdma_rlc_reg_offset()
298 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + in kgd_hqd_sdma_dump()
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| A D | amdgpu_amdkfd_gfx_v8.c | 135 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + in get_sdma_rlc_reg_offset()
321 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + in kgd_hqd_sdma_dump()
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| A D | vid.h | 27 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ macro
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| A D | cikd.h | 492 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ macro
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| A D | cik.c | 1053 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
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| A D | vi.c | 677 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
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