| /drivers/gpu/drm/xe/ |
| A D | xe_wa.c | 209 SET(XEHPC_L3CLOS_MASK(1), ~0),
210 SET(XEHPC_L3CLOS_MASK(2), ~0),
211 SET(XEHPC_L3CLOS_MASK(3), ~0))
767 XE_RTP_ACTIONS(SET(FF_MODE,
771 SET(VFLSKPD,
813 XE_RTP_ACTIONS(SET(FF_MODE,
816 SET(VFLSKPD,
840 XE_RTP_ACTIONS(SET(FF_MODE,
843 SET(VFLSKPD,
864 XE_RTP_ACTIONS(SET(FF_MODE,
[all …]
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| A D | xe_tuning.c | 27 XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS))
45 SET(CCCHKNREG1, L3CMPCTRL))
50 SET(XE2LPM_CCCHKNREG1, L3CMPCTRL))
54 XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
58 XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3, COMPPWOVERFETCHEN))
62 XE_RTP_ACTIONS(SET(L3SQCREG2,
67 XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
82 XE_RTP_ACTIONS(SET(SCRATCH3_LBCF, RWFLUSHALLEN))
86 XE_RTP_ACTIONS(SET(XE2LPM_SCRATCH3_LBCF, RWFLUSHALLEN))
104 XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))
[all …]
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| A D | xe_hw_engine.c | 456 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ, in hw_engine_setup_default_state()
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| /drivers/gpu/drm/xe/tests/ |
| A D | xe_rtp_test.c | 73 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
77 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
93 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
97 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
112 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
118 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
122 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(2)))
126 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(3)))
138 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(0)))
147 XE_RTP_ACTIONS(SET(REGULAR_REG1, REG_BIT(1)))
[all …]
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| /drivers/gpu/drm/sti/ |
| A D | sti_awg_utils.c | 17 SET, enumerator
69 opcode = SET; in awg_generate_instr()
97 case SET: in awg_generate_instr()
138 ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, in awg_generate_line_signal()
148 ret |= awg_generate_instr(SET, val, 0, 0, fwparams); in awg_generate_line_signal()
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| /drivers/clk/imx/ |
| A D | clk-pfd.c | 32 #define SET 0x4 macro
49 writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); in clk_pfd_disable()
103 writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET); in clk_pfd_set_rate()
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| /drivers/clk/mxs/ |
| A D | clk-pll.c | 36 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
63 writel_relaxed(1 << 31, pll->base + SET); in clk_pll_disable()
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| A D | clk-imx28.c | 74 writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET); in mxs_saif_clkmux_select()
84 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); in clk_misc_init()
87 writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET); in clk_misc_init()
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| A D | clk-imx23.c | 49 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); in clk_misc_init()
70 writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET); in clk_misc_init()
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| A D | clk.h | 14 #define SET 0x4 macro
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| A D | clk-ref.c | 44 writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET); in clk_ref_disable()
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| /drivers/pwm/ |
| A D | pwm-mxs.c | 17 #define SET 0x4 macro
110 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET); in mxs_pwm_apply()
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| /drivers/gpu/drm/imx/dcss/ |
| A D | dcss-dev.h | 15 #define SET 0x04 macro
21 #define dcss_set(v, c) writel((v), (c) + SET)
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| /drivers/pinctrl/freescale/ |
| A D | pinctrl-mxs.h | 12 #define SET 0x4 macro
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| A D | pinctrl-mxs.c | 294 writel(1 << shift, reg + SET); in mxs_pinconf_group_set()
305 writel(1 << shift, reg + SET); in mxs_pinconf_group_set()
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| /drivers/scsi/ |
| A D | 53c700.scr | 164 SET TARGET
239 SET ATN
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| A D | 53c700_d.h_shipped | 200 SET TARGET
395 SET ATN
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| /drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| A D | ctxnv50.c | 196 cp_set (ctx, UNK01, SET); in nv50_grctx_generate()
202 cp_bra (ctx, UNK0B, SET, cp_prepare_exit); in nv50_grctx_generate()
207 cp_set (ctx, UNK1D, SET); in nv50_grctx_generate()
211 cp_set (ctx, UNK01, SET); in nv50_grctx_generate()
216 cp_set (ctx, UNK03, SET); in nv50_grctx_generate()
226 cp_set (ctx, UNK20, SET); in nv50_grctx_generate()
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| /drivers/net/fddi/skfp/h/ |
| A D | skfbi.h | 805 #define SET(io,mask) outpw((io),inpw(io)|(mask)) macro
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| /drivers/accel/ivpu/ |
| A D | ivpu_hw_ip.c | 1154 u32 val = REG_FLD(VPU_37XX_CPU_SS_DOORBELL_0, SET); in db_set_37xx()
1162 u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET); in db_set_40xx()
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| /drivers/net/wireless/mediatek/mt76/mt7996/ |
| A D | debugfs.c | 370 return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), MCU_WA_PARAM_PDMA_RX, in mt7996_fw_debug_wa_set()
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| A D | init.c | 596 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), in mt7996_mac_init()
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| /drivers/net/wireless/mediatek/mt76/mt7915/ |
| A D | debugfs.c | 584 ret = mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), in mt7915_fw_debug_wa_set()
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| A D | mcu.c | 2355 return mt76_mcu_send_msg(&dev->mt76, MCU_WA_PARAM_CMD(SET), &req, in mt7915_red_set_watermark()
2378 return mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), in mt7915_mcu_set_red()
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| /drivers/net/ethernet/mellanox/mlxsw/ |
| A D | spectrum_router.c | 8475 #define MLXSW_SP_ROUTER_ALL_GOOD(SET, SFX) \ in mlxsw_sp_router_port_l3_stats_fetch() argument
8476 ((SET.good_unicast_ ## SFX) + \ in mlxsw_sp_router_port_l3_stats_fetch()
8477 (SET.good_multicast_ ## SFX) + \ in mlxsw_sp_router_port_l3_stats_fetch()
8478 (SET.good_broadcast_ ## SFX)) in mlxsw_sp_router_port_l3_stats_fetch()
|