| /drivers/gpu/drm/amd/display/dc/dwb/dcn30/ |
| A D | dcn30_dwb.h | 151 SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_EYE_SELECTION, mask_sh),\
153 SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_NEW_CONTENT, mask_sh),\
164 SF_DWB2(DWB_CRC_CTRL, DWB_TOP, 0, DWB_CRC_EN, mask_sh),\
165 SF_DWB2(DWB_CRC_CTRL, DWB_TOP, 0, DWB_CRC_CONT_EN, mask_sh),\
166 SF_DWB2(DWB_CRC_CTRL, DWB_TOP, 0, DWB_CRC_SRC_SEL, mask_sh),\
174 SF_DWB2(DWB_CRC_VAL_B_A, DWB_TOP, 0, DWB_CRC_SIG_A, mask_sh),\
175 SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_FORMAT, mask_sh),\
176 SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_DENORM, mask_sh),\
177 SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_MAX, mask_sh),\
178 SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_MIN, mask_sh),\
[all …]
|
| /drivers/gpu/drm/amd/display/dc/dwb/dcn35/ |
| A D | dcn35_dwb.h | 36 SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DWB_FGCG_REP_DIS, mask_sh)
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| A D | dcn302_resource.c | 203 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ macro
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| /drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| A D | dcn303_resource.c | 200 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ macro
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| /drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| A D | dcn301_resource.c | 149 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ macro
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| A D | dcn316_resource.c | 176 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ macro
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| A D | dcn314_resource.c | 173 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ macro
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| A D | dcn31_resource.c | 156 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ macro
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 176 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ macro
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.c | 188 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ macro
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| A D | dcn315_resource.c | 190 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ macro
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 168 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ macro
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| A D | dcn36_resource.c | 173 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ macro
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| A D | dcn30_resource.c | 145 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ macro
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 163 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ macro
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 142 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ macro
|
| /drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.c | 172 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ macro
|