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Searched refs:SKL_DPLL0 (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_cdclk.c982 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | in skl_dpll0_update()
983 DPLL_CTRL1_SSC(SKL_DPLL0) | in skl_dpll0_update()
984 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != in skl_dpll0_update()
985 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) in skl_dpll0_update()
988 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { in skl_dpll0_update()
989 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): in skl_dpll0_update()
1000 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); in skl_dpll0_update()
1104 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | in skl_dpll0_enable()
1105 DPLL_CTRL1_SSC(SKL_DPLL0) | in skl_dpll0_enable()
1106 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), in skl_dpll0_enable()
[all …]
A Dintel_dpll_mgr.h385 #define SKL_DPLL0 0 macro

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