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Searched refs:SNPS_PHY_MPLLB_CP_INT (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_snps_phy.c100 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
127 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
149 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
170 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
190 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
225 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
273 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
304 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
335 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
367 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
[all …]
A Dintel_snps_phy_regs.h23 #define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25) macro
A Dintel_snps_hdmi_pll.c266 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, pll_params.ana_cp_int) | in intel_snps_hdmi_pll_compute_mpllb()

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