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Searched refs:SNPS_PHY_MPLLB_CP_INT_GS (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_snps_phy.c102 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
129 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
151 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
172 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
192 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
227 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
275 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
306 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
337 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
369 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
[all …]
A Dintel_snps_phy_regs.h24 #define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17) macro
A Dintel_snps_hdmi_pll.c268 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, ana_cp_int_gs) | in intel_snps_hdmi_pll_compute_mpllb()

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