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Searched refs:SNPS_PHY_MPLLB_REF_CLK_DIV (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_snps_phy.c111 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
137 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
158 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
178 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
204 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
238 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
283 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
314 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
346 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
377 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
[all …]
A Dintel_snps_phy_regs.h61 #define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12) macro
A Dintel_snps_hdmi_pll.c277 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, prescaler_divider) | in intel_snps_hdmi_pll_compute_mpllb()

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