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Searched refs:SNPS_PHY_MPLLB_TX_CLK_DIV (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_snps_phy.c106 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
133 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
279 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
310 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
341 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
373 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
420 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
449 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
478 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
508 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
[all …]
A Dintel_snps_phy_regs.h38 #define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5) macro
A Dintel_snps_hdmi_pll.c272 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_params.tx_clk_div) | in intel_snps_hdmi_pll_compute_mpllb()

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