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Searched refs:SNPS_PHY_REF_CONTROL_REF_RANGE (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_snps_phy.c98 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
125 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
147 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
168 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
188 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
223 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
271 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
302 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
333 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
365 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
[all …]
A Dintel_snps_phy_regs.h65 #define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27) macro
A Dintel_snps_hdmi_pll.c264 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, ref_range); in intel_snps_hdmi_pll_compute_mpllb()

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