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Searched refs:SOC15_REG_ENTRY (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dmmhub_v9_4.c1566 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 0, 0, 0 },
1567 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 0, 0, 0 },
1568 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 0, 0, 0 },
1569 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 0, 0, 0 },
1570 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 0, 0, 0 },
1572 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 0, 0, 0 },
1575 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 0, 0, 0 },
1578 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 0, 0, 0 },
1581 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 0, 0, 0 },
1584 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 0, 0, 0 },
[all …]
A Dgfx_v9_4.c51 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1 },
57 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1 },
59 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 8, 16 },
131 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
135 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
139 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
143 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
175 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
179 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
183 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
[all …]
A Dgfx_v9_4_2.c897 SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
901 SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
905 SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
909 SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
930 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
934 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
938 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
942 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
946 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
949 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
[all …]
A Dmmhub_v1_7.c1211 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 0, 0, 0 },
1212 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 0, 0, 0 },
1213 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 0, 0, 0 },
1214 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 0, 0, 0 },
1215 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 0, 0, 0 },
1216 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 0, 0, 0 },
1217 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 0, 0, 0 },
1218 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 0, 0, 0 },
1220 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 0, 0, 0 },
1223 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 0, 0, 0 },
[all …]
A Dsdma_v4_4.c60 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
64 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
68 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
72 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
76 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
80 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
84 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
124 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
128 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
132 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
[all …]
A Dmmhub_v1_0.c640 { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
644 { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
656 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
660 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
700 { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
704 { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
716 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
751 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 0, 0, 0},
752 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 0, 0, 0},
753 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 0, 0, 0},
[all …]
A Dsoc24.c114 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
115 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
116 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
117 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
118 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
119 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
122 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
123 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
128 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
131 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
[all …]
A Dgfx_v9_0.c875 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)},
876 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)},
6336 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
6349 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
6354 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
6359 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
6364 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
6369 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
6374 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
6526 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
[all …]
A Dsoc21.c251 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
252 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
253 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
254 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
255 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
256 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
259 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
260 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
265 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
268 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
[all …]
A Dnv.c336 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
337 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
338 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
339 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
340 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
341 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
344 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
345 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
350 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
353 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
[all …]
A Dsoc15.c382 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
383 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
384 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
385 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
386 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
387 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
390 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
396 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
399 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
400 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
[all …]
A Dsdma_v4_0.c343 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
347 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
351 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
355 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
363 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
367 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
371 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
375 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
379 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
383 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
[all …]
A Dsoc15.h90 #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg macro
A Dgfx_v9_4_3.c1690 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)},
1691 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)},
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega10_baco.c36 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIF_FB_EN), 0, 0, 0, 0},
43 …{CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_EN_MASK, BACO_CNTL__B…
45 …{CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_DUMMY_EN_MASK, BACO_C…
52 …{CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_POWER_OFF_MASK, BACO_…
56 …{CMD_WAITFOR, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_MODE_MASK, BACO_CNTL__BACO_MO…
60 …{CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_POWER_OFF_MASK, BACO_…
71 …{CMD_WAITFOR, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_EXIT_MASK, 0, 0xffffff…
75 …{CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_EN_MASK, BACO_CNTL__B…
76 {CMD_WAITFOR, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0}
80 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
[all …]
A Dvega20_baco.c35 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
36 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},

Completed in 58 milliseconds