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Searched refs:SOC15_REG_ENTRY_STR (Results 1 – 25 of 28) sorted by relevance

12

/drivers/gpu/drm/amd/amdgpu/
A Djpeg_v5_0_1.c59 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
60 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
61 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR),
63 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS),
64 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
68 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),
69 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),
72 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS),
75 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS),
78 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS),
[all …]
A Dsdma_v7_0.c63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),
64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG),
68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG),
69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG),
70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_REV),
114 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS),
115 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_VM_CNTL),
[all …]
A Dsdma_v6_0.c64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG),
68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG),
69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG),
70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG),
73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH),
115 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS),
116 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
[all …]
A Dgfx_v12_0.c86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
107 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
123 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
124 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
129 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
[all …]
A Dsdma_v5_2.c64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),
78 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),
80 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),
85 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),
107 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS),
108 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL),
[all …]
A Dsdma_v5_0.c63 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
76 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),
77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),
79 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),
84 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),
106 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS),
107 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL),
[all …]
A Djpeg_v4_0_3.c63 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
64 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
65 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_SYS_INT_STATUS),
68 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS),
69 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
73 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),
74 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),
77 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS),
80 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS),
83 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS),
[all …]
A Djpeg_v3_0.c38 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
39 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),
40 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),
41 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),
42 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),
43 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),
44 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),
45 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),
46 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),
49 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH),
[all …]
A Dgfx_v11_0.c125 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
141 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
142 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
143 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
144 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
145 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
146 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
147 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE),
168 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
169 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
[all …]
A Dgfx_v9_0.c154 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
165 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
166 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
167 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
168 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
169 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
170 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
171 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
172 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
210 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
[all …]
A Dvcn_v5_0_0.c42 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
[all …]
A Djpeg_v5_0_0.c38 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
39 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
40 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),
41 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),
42 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),
43 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),
44 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),
45 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
46 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),
49 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),
[all …]
A Dvcn_v4_0_5.c58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
[all …]
A Dsdma_v4_0.c76 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
78 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
79 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
89 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),
90 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),
92 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),
97 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),
98 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),
101 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL),
[all …]
A Dsdma_v4_4_2.c52 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG),
53 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG),
54 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG),
55 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL),
66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR),
68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR),
73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL),
74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR),
77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL),
[all …]
A Dgfx_v9_4_3.c68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
78 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT),
106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT),
[all …]
A Dgfx_v10_0.c280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
295 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
296 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
297 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
298 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
299 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
300 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
301 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
302 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
340 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
[all …]
A Djpeg_v2_0.c37 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
38 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),
39 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),
40 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),
41 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),
42 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),
43 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),
44 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),
45 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),
48 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH),
[all …]
A Djpeg_v4_0.c40 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
41 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
42 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),
43 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),
44 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),
45 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),
46 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),
47 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
48 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),
51 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),
[all …]
A Djpeg_v4_0_5.c50 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
51 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
52 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),
53 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),
54 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),
55 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),
56 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),
57 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
58 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),
61 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),
[all …]
A Djpeg_v2_5.c40 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
41 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),
42 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),
43 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),
44 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),
45 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),
46 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),
47 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),
48 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),
51 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH),
[all …]
A Dvcn_v1_0.c50 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),
65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),
69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),
70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),
71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
[all …]
A Dvcn_v4_0_3.c52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
[all …]
A Dvcn_v2_0.c59 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),
74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),
78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),
79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),
80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
[all …]
A Dvcn_v4_0.c58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
[all …]

Completed in 134 milliseconds

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