| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_shared_types.h | 355 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state member
826 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state member
1146 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state member
1709 double SOCCLK; member
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| A D | dml2_core_dcn4.c | 433 …ode_support_result.global.socclk_khz = (unsigned int)(core->clean_me_up.mode_lib.ms.SOCCLK * 1000); in core_dcn4_mode_support()
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| A D | dml2_core_dcn4_calcs.c | 6724 …atermark = p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6733 …eLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6734 …hangeLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024 / 32 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
7878 CalculateWatermarks_params->SOCCLK = mode_lib->ms.SOCCLK; in dml_core_ms_prefetch_check()
7940 mode_lib->ms.SOCCLK = ((double)mode_lib->soc.clk_table.socclk.clk_values_khz[0] / 1000); in dml_core_mode_support()
7959 DML_LOG_VERBOSE("DML::%s: SOCCLK = %f\n", __func__, mode_lib->ms.SOCCLK); in dml_core_mode_support()
10379 s->SOCCLK = (double)programming->min_clocks.dcn4x.socclk_khz / 1000; in dml_core_mode_programming()
10436 DML_ASSERT(s->SOCCLK > 0); in dml_core_mode_programming()
10451 DML_LOG_VERBOSE("DML::%s: SOCCLK = %f\n", __func__, s->SOCCLK); in dml_core_mode_programming()
11673 CalculateWatermarks_params->SOCCLK = s->SOCCLK; in dml_core_mode_programming()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_mode_vba_util_32.h | 810 double SOCCLK,
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| A D | display_mode_vba_util_32.c | 4265 double SOCCLK, in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport() argument
4363 + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
4376 + mmSOCParameters.WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
4378 + mmSOCParameters.WritebackLatency + v->WritebackChunkSize * 1024 / 32 / SOCCLK; in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_vba.c | 381 mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()
1094 mode_lib->vba.SOCCLK = mode_lib->vba.cache_pipes[0].clks_cfg.socclk_mhz; in ModeSupportAndSystemConfiguration()
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| A D | display_mode_vba.h | 437 double SOCCLK; member
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | display_mode_core_structs.h | 834 dml_float_t SOCCLK; /// <brief Basically just the clock freq at the min (or given) state member
1347 dml_float_t SOCCLK; member
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| A D | display_mode_core.c | 2862 …atermark = p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
2871 …eLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
2872 …hangeLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024 / 32 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6665 CalculateWatermarks_params->SOCCLK = mode_lib->ms.state.socclk_mhz; in dml_prefetch_check()
8239 mode_lib->ms.SOCCLK = mode_lib->ms.state.socclk_mhz; in dml_core_mode_support()
8333 dml_print("DML::%s: Using SOCCLK = %f\n", __func__, mode_lib->ms.SOCCLK); in dml_core_mode_programming()
9430 CalculateWatermarks_params->SOCCLK = mode_lib->ms.SOCCLK; in dml_core_mode_programming()
10076 mode_lib->ms.SOCCLK = (dml_float_t)state->socclk_mhz; in fetch_socbb_params()
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| /drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| A D | smu_v13_0_5_ppt.c | 112 FEA_MAP_REVERSE(SOCCLK),
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| A D | smu_v13_0_4_ppt.c | 117 FEA_MAP_REVERSE(SOCCLK),
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| A D | yellow_carp_ppt.c | 112 FEA_MAP_REVERSE(SOCCLK),
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| A D | aldebaran_ppt.c | 160 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| A D | smu_v13_0_7_ppt.c | 151 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_mode_vba_21.c | 305 double SOCCLK,
2434 mode_lib->vba.SOCCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5223 mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel]; in dml21_ModeSupportAndSystemConfigurationFull()
5259 double SOCCLK, in CalculateWatermarksAndDRAMSpeedChangeSupport() argument
5348 + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; in CalculateWatermarksAndDRAMSpeedChangeSupport()
5355 + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; in CalculateWatermarksAndDRAMSpeedChangeSupport()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_mode_vba_30.c | 312 double SOCCLK,
2748 v->SOCCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5173 v->SOCCLK = v->SOCCLKPerState[v->VoltageLevel]; in dml30_ModeSupportAndSystemConfigurationFull()
5197 double SOCCLK, in CalculateWatermarksAndDRAMSpeedChangeSupport() argument
5280 *WritebackUrgentWatermark = WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; in CalculateWatermarksAndDRAMSpeedChangeSupport()
5286 …atermark = DRAMClockChangeLatency + WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; in CalculateWatermarksAndDRAMSpeedChangeSupport()
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| /drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| A D | renoir_ppt.c | 118 CLK_MAP(SOCCLK, CLOCK_SOCCLK),
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_mode_vba_31.c | 299 double SOCCLK,
2942 v->SOCCLK,
5537 v->SOCCLK = v->SOCCLKPerState[v->VoltageLevel];
5550 double SOCCLK, argument
5612 …v->WritebackUrgentWatermark = v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
5618 …= v->DRAMClockChangeLatency + v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_mode_vba_314.c | 308 double SOCCLK,
2961 v->SOCCLK,
5631 v->SOCCLK = v->SOCCLKPerState[v->VoltageLevel];
5644 double SOCCLK, argument
5706 …v->WritebackUrgentWatermark = v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
5712 …= v->DRAMClockChangeLatency + v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
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| /drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| A D | smu_v14_0_0_ppt.c | 154 FEA_MAP_REVERSE(SOCCLK),
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| A D | smu_v14_0_2_ppt.c | 144 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_mode_vba_20.c | 1499 / mode_lib->vba.SOCCLK; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1511 DTRACE(" socclk frequency %f Mhz", mode_lib->vba.SOCCLK); in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1522 / mode_lib->vba.SOCCLK; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5100 mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel]; in dml20_ModeSupportAndSystemConfigurationFull()
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| A D | display_mode_vba_20v2.c | 1535 / mode_lib->vba.SOCCLK; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1547 DTRACE(" socclk frequency %f Mhz", mode_lib->vba.SOCCLK); in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1558 / mode_lib->vba.SOCCLK; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5216 mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel]; in dml20v2_ModeSupportAndSystemConfigurationFull()
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| /drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| A D | arcturus_ppt.c | 167 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| A D | vangogh_ppt.c | 188 FEA_MAP_REVERSE(SOCCLK),
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