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Searched refs:SRII (Results 1 – 25 of 36) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clock_source.h60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
90 SRII(PHASE, DP_DTO, 0),\
91 SRII(PHASE, DP_DTO, 1),\
[all …]
/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
A Ddcn32_mpc.h37 SRII(MPCC_MCM_SHAPER_CONTROL, MPCC_MCM, inst),\
38 SRII(MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM, inst),\
39 SRII(MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM, inst),\
40 SRII(MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM, inst),\
41 SRII(MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM, inst),\
42 SRII(MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM, inst),\
44 SRII(MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM, inst),\
93 SRII(MPCC_MCM_3DLUT_INDEX, MPCC_MCM, inst),\
94 SRII(MPCC_MCM_3DLUT_DATA, MPCC_MCM, inst),\
101 SRII(MPCC_MCM_1DLUT_CONTROL, MPCC_MCM, inst),\
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.h785 SRII(CSC_C11_C12_A, MPC_OUT, inst), SRII(CSC_C33_C34_A, MPC_OUT, inst), \
786 SRII(CSC_C11_C12_B, MPC_OUT, inst), SRII(CSC_C33_C34_B, MPC_OUT, inst), \
792 SRII(MPCC_TOP_SEL, MPCC, inst), SRII(MPCC_BOT_SEL, MPCC, inst), \
793 SRII(MPCC_CONTROL, MPCC, inst), SRII(MPCC_STATUS, MPCC, inst), \
794 SRII(MPCC_OPP_ID, MPCC, inst), SRII(MPCC_BG_G_Y, MPCC, inst), \
795 SRII(MPCC_BG_R_CR, MPCC, inst), SRII(MPCC_BG_B_CB, MPCC, inst), \
797 SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
914 SRII(MPCC_MCM_3DLUT_INDEX, MPCC_MCM, inst),\
915 SRII(MPCC_MCM_3DLUT_DATA, MPCC_MCM, inst),\
922 SRII(MPCC_MCM_1DLUT_CONTROL, MPCC_MCM, inst),\
[all …]
A Ddcn32_resource.c156 #define SRII(reg_name, block, id)\ macro
540 SRII(PIXEL_RATE_CNTL, OTG, 0), \
541 SRII(PIXEL_RATE_CNTL, OTG, 1),\
542 SRII(PIXEL_RATE_CNTL, OTG, 2),\
543 SRII(PIXEL_RATE_CNTL, OTG, 3),\
544 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
545 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
546 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
547 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
A Ddcn20_mpc.h35 SRII(MPCC_TOP_GAIN, MPCC, inst),\
36 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
66 SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
70 SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst)
74 SRII(CSC_MODE, MPC_OUT, inst),\
75 SRII(CSC_C11_C12_A, MPC_OUT, inst),\
76 SRII(CSC_C33_C34_A, MPC_OUT, inst),\
77 SRII(CSC_C11_C12_B, MPC_OUT, inst),\
78 SRII(CSC_C33_C34_B, MPC_OUT, inst),\
79 SRII(DENORM_CONTROL, MPC_OUT, inst),\
[all …]
/drivers/gpu/drm/amd/display/dc/mpc/dcn30/
A Ddcn30_mpc.h47 SRII(MPCC_TOP_GAIN, MPCC, inst),\
48 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
50 SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
104 SRII(CSC_MODE, MPC_OUT, inst),\
105 SRII(CSC_C11_C12_A, MPC_OUT, inst),\
106 SRII(CSC_C33_C34_A, MPC_OUT, inst),\
107 SRII(CSC_C11_C12_B, MPC_OUT, inst),\
108 SRII(CSC_C33_C34_B, MPC_OUT, inst),\
109 SRII(DENORM_CONTROL, MPC_OUT, inst),\
119 SRII(SHAPER_CONTROL, MPC_RMU, inst),\
[all …]
/drivers/gpu/drm/amd/display/dc/mpc/dcn401/
A Ddcn401_mpc.h109 SRII(MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM, inst),\
110 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM, inst),\
111 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM, inst),\
112 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM, inst),\
113 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM, inst),\
114 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM, inst),\
115 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM, inst),\
116 SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B, MPCC_MCM, inst),\
123 SRII(MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM, inst), \
136 SRII(MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM, inst),\
[all …]
/drivers/gpu/drm/amd/display/dc/hwss/dce/
A Ddce_hwseq.h54 SRII(BLND_CONTROL, BLND, 0), \
55 SRII(BLND_CONTROL, BLND, 1), \
56 SRII(BLND_CONTROL, BLND, 2), \
57 SRII(BLND_CONTROL, BLND, 3), \
58 SRII(BLND_CONTROL, BLND, 4), \
59 SRII(BLND_CONTROL, BLND, 5)
71 SRII(PIXEL_RATE_CNTL, blk, 5)
75 SRII(PIXEL_RATE_CNTL, blk, 1)
91 SRII(PIXEL_RATE_CNTL, blk, 5)
106 SRII(PIXEL_RATE_CNTL, blk, 4)
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn36/
A Ddcn36_resource.h35 SRII(PIXEL_RATE_CNTL, OTG, 0), \
36 SRII(PIXEL_RATE_CNTL, OTG, 1),\
37 SRII(PIXEL_RATE_CNTL, OTG, 2),\
38 SRII(PIXEL_RATE_CNTL, OTG, 3),\
39 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
40 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
41 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
42 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/drivers/gpu/drm/amd/display/dc/mpc/dcn10/
A Ddcn10_mpc.h34 SRII(MPCC_TOP_SEL, MPCC, inst),\
35 SRII(MPCC_BOT_SEL, MPCC, inst),\
36 SRII(MPCC_CONTROL, MPCC, inst),\
37 SRII(MPCC_STATUS, MPCC, inst),\
38 SRII(MPCC_OPP_ID, MPCC, inst),\
39 SRII(MPCC_BG_G_Y, MPCC, inst),\
40 SRII(MPCC_BG_R_CR, MPCC, inst),\
41 SRII(MPCC_BG_B_CB, MPCC, inst),\
42 SRII(MPCC_SM_CONTROL, MPCC, inst),\
43 SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
[all …]
/drivers/gpu/drm/amd/display/dc/resource/dcn35/
A Ddcn35_resource.h174 SRII(PIXEL_RATE_CNTL, OTG, 0), \
175 SRII(PIXEL_RATE_CNTL, OTG, 1),\
176 SRII(PIXEL_RATE_CNTL, OTG, 2),\
177 SRII(PIXEL_RATE_CNTL, OTG, 3),\
178 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
179 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
180 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
181 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/drivers/gpu/drm/amd/display/dc/resource/dcn316/
A Ddcn316_resource.c164 #define SRII(reg_name, block, id)\ macro
683 SRII(PIXEL_RATE_CNTL, OTG, 0), \
684 SRII(PIXEL_RATE_CNTL, OTG, 1),\
685 SRII(PIXEL_RATE_CNTL, OTG, 2),\
686 SRII(PIXEL_RATE_CNTL, OTG, 3),\
687 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
688 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
689 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
690 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/drivers/gpu/drm/amd/display/dc/resource/dcn314/
A Ddcn314_resource.c161 #define SRII(reg_name, block, id)\ macro
696 SRII(PIXEL_RATE_CNTL, OTG, 0), \
697 SRII(PIXEL_RATE_CNTL, OTG, 1),\
698 SRII(PIXEL_RATE_CNTL, OTG, 2),\
699 SRII(PIXEL_RATE_CNTL, OTG, 3),\
700 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
701 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
702 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
703 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/drivers/gpu/drm/amd/display/dc/resource/dcn31/
A Ddcn31_resource.c144 #define SRII(reg_name, block, id)\ macro
689 SRII(PIXEL_RATE_CNTL, OTG, 0), \
690 SRII(PIXEL_RATE_CNTL, OTG, 1),\
691 SRII(PIXEL_RATE_CNTL, OTG, 2),\
692 SRII(PIXEL_RATE_CNTL, OTG, 3),\
693 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
695 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
696 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/drivers/gpu/drm/amd/display/dc/resource/dcn321/
A Ddcn321_resource.c156 #define SRII(reg_name, block, id)\ macro
536 SRII(PIXEL_RATE_CNTL, OTG, 0), \
537 SRII(PIXEL_RATE_CNTL, OTG, 1),\
538 SRII(PIXEL_RATE_CNTL, OTG, 2),\
539 SRII(PIXEL_RATE_CNTL, OTG, 3),\
540 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
541 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
542 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/drivers/gpu/drm/amd/display/dc/resource/dcn315/
A Ddcn315_resource.c178 #define SRII(reg_name, block, id)\ macro
688 SRII(PIXEL_RATE_CNTL, OTG, 0), \
689 SRII(PIXEL_RATE_CNTL, OTG, 1),\
690 SRII(PIXEL_RATE_CNTL, OTG, 2),\
691 SRII(PIXEL_RATE_CNTL, OTG, 3),\
692 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
693 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
695 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.c143 #define SRII(reg_name, block, id)\ macro
515 SRII(PIXEL_RATE_CNTL, OTG, 0), \
516 SRII(PIXEL_RATE_CNTL, OTG, 1),\
517 SRII(PIXEL_RATE_CNTL, OTG, 2),\
518 SRII(PIXEL_RATE_CNTL, OTG, 3),\
519 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
520 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
521 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
522 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/drivers/gpu/drm/amd/display/dc/hpo/dcn31/
A Ddcn31_hpo_dp_link_encoder.h68 SRII(RDPCSTX_PHY_CNTL6, RDPCSTX, id)
/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_dwb.h43 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dce100/
A Ddce100_resource.c491 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dce120/
A Ddce120_resource.c780 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dcn201/
A Ddcn201_resource.c263 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dce112/
A Ddce112_resource.c521 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dce60/
A Ddce60_resource.c607 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/resource/dce80/
A Ddce80_resource.c613 #define SRII(reg_name, block, id)\ macro

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