Home
last modified time | relevance | path

Searched refs:SSPP_VIG2 (Results 1 – 21 of 21) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_top.c98 status->sspp[SSPP_VIG2] = (value >> 8) & 0x3; in dpu_hw_get_danger_status()
210 status->sspp[SSPP_VIG2] = (value >> 8) & 0x1; in dpu_hw_get_safe_status()
A Ddpu_hw_mdss.h95 SSPP_VIG2, enumerator
A Ddpu_hw_ctl.c199 case SSPP_VIG2: in dpu_hw_ctl_update_pending_flush_sspp()
488 [SSPP_VIG2] = { { 0, 6, 4 }, { 3, 8 } },
/drivers/gpu/drm/msm/disp/mdp5/
A Dmdp5_cfg.c28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
198 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
287 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
539 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
A Dmdp5_ctl.c295 case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage); in mdp_ctl_blend_mask()
318 case SSPP_VIG2: return MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3; in mdp_ctl_blend_ext_mask()
446 case SSPP_VIG2: return MDP5_CTL_FLUSH_VIG2; in mdp_ctl_flush_mask_pipe()
A Dmdp5_kms.c607 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init() enumerator
/drivers/gpu/drm/msm/disp/dpu1/catalog/
A Ddpu_1_7_msm8996.h79 .name = "sspp_2", .id = SSPP_VIG2,
A Ddpu_3_0_msm8998.h84 .name = "sspp_2", .id = SSPP_VIG2,
A Ddpu_4_0_sdm845.h82 .name = "sspp_2", .id = SSPP_VIG2,
A Ddpu_5_0_sm8150.h85 .name = "sspp_2", .id = SSPP_VIG2,
A Ddpu_6_0_sm8250.h84 .name = "sspp_2", .id = SSPP_VIG2,
A Ddpu_7_0_sm8350.h84 .name = "sspp_2", .id = SSPP_VIG2,
A Ddpu_9_0_sm8550.h73 .name = "sspp_2", .id = SSPP_VIG2,
A Ddpu_9_1_sar2130p.h73 .name = "sspp_2", .id = SSPP_VIG2,
A Ddpu_10_0_sm8650.h73 .name = "sspp_2", .id = SSPP_VIG2,
A Ddpu_8_0_sc8280xp.h83 .name = "sspp_2", .id = SSPP_VIG2,
A Ddpu_8_1_sm8450.h84 .name = "sspp_2", .id = SSPP_VIG2,
A Ddpu_5_1_sc8180x.h85 .name = "sspp_2", .id = SSPP_VIG2,
A Ddpu_9_2_x1e80100.h72 .name = "sspp_2", .id = SSPP_VIG2,
A Ddpu_8_4_sa8775p.h83 .name = "sspp_2", .id = SSPP_VIG2,
A Ddpu_12_0_sm8750.h74 .name = "sspp_2", .id = SSPP_VIG2,

Completed in 24 milliseconds