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Searched refs:SW_IRQ_CLR_DP_TRANS_P0_MASK (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/mediatek/
A Dmtk_dp_reg.h290 #define SW_IRQ_CLR_DP_TRANS_P0_MASK GENMASK(15, 0) macro
A Dmtk_dp.c1007 irq_status, SW_IRQ_CLR_DP_TRANS_P0_MASK); in mtk_dp_swirq_get_clear()
1009 0, SW_IRQ_CLR_DP_TRANS_P0_MASK); in mtk_dp_swirq_get_clear()

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