Searched refs:SW_MODE (Results 1 – 10 of 10) sorted by relevance
| /drivers/mtd/devices/ |
| A D | spear_smi.c | 60 #define SW_MODE (0x1 << 28) /* enables SW Mode */ macro
231 writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1); in spear_smi_read_sr()
389 writel(ctrlreg1 & ~SW_MODE, dev->io_base + SMI_CR1); in spear_smi_write_enable()
461 writel((ctrlreg1 | SW_MODE) & ~WB_MODE, dev->io_base + SMI_CR1); in spear_smi_erase_sector()
577 val &= ~(SW_MODE | WB_MODE); in spear_mtd_read()
635 writel((ctrlreg1 | WB_MODE) & ~SW_MODE, dev->io_base + SMI_CR1); in spear_smi_cpy_toio()
759 writel(val | SW_MODE, dev->io_base + SMI_CR1); in spear_smi_probe_flash()
784 writel(val & ~SW_MODE, dev->io_base + SMI_CR1); in spear_smi_probe_flash()
|
| /drivers/gpu/drm/amd/display/dc/hubp/dcn30/ |
| A D | dcn30_hubp.c | 331 SW_MODE, info->gfx9.swizzle, in hubp3_program_tiling()
342 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR); in hubp3_clear_tiling()
|
| A D | dcn30_hubp.h | 70 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
|
| /drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| A D | dcn401_hubp.c | 528 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR); in hubp401_clear_tiling()
555 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx_addr3.swizzle); in hubp401_program_tiling()
945 SW_MODE, &s->sw_mode); in hubp401_read_state()
|
| A D | dcn401_hubp.h | 65 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
|
| /drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| A D | dcn10_hubp.c | 157 SW_MODE, info->gfx9.swizzle, in hubp1_program_tiling()
526 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR); in hubp1_clear_tiling()
1059 SW_MODE, &s->sw_mode); in hubp1_read_state_common()
|
| A D | dcn10_hubp.h | 274 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
472 type SW_MODE;\
|
| /drivers/gpu/drm/amd/display/dc/hubp/dcn31/ |
| A D | dcn31_hubp.h | 54 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
|
| /drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| A D | dcn20_hubp.c | 322 SW_MODE, info->gfx9.swizzle, in hubp2_program_tiling()
414 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR); in hubp2_clear_tiling()
1290 SW_MODE, &s->sw_mode); in hubp2_read_state_common()
|
| /drivers/gpu/drm/amd/include/ |
| A D | navi10_enum.h | 1561 typedef enum SW_MODE { enum
1578 } SW_MODE; typedef
|
Completed in 112 milliseconds