Searched refs:SW_RST (Results 1 – 8 of 8) sorted by relevance
| /drivers/thermal/qcom/ |
| A D | tsens-8960.c | 25 #define SW_RST BIT(1) macro
86 ret = regmap_update_bits(map, CNTL_ADDR, SW_RST, SW_RST); in resume_8960()
136 ret = regmap_write(priv->tm_map, CNTL_ADDR, reg | SW_RST); in enable_8960()
|
| /drivers/char/hw_random/ |
| A D | airoha-trng.c | 22 #define SW_RST BIT(0) /* Active High */ macro
135 writel(SW_RST, trng->base + TRNG_HEALTH_TEST_SW_RST); in airoha_trng_cleanup()
208 writel(SW_RST, trng->base + TRNG_HEALTH_TEST_SW_RST); in airoha_trng_probe()
|
| /drivers/clk/imx/ |
| A D | clk-composite-7ulp.c | 26 #define SW_RST BIT(28) macro
45 val |= SW_RST; in pcc_gate_enable()
|
| /drivers/net/ethernet/moxa/ |
| A D | moxart_ether.c | 93 writel(SW_RST, priv->base + REG_MAC_CTRL); in moxart_mac_reset()
94 while (readl(priv->base + REG_MAC_CTRL) & SW_RST) in moxart_mac_reset()
|
| A D | moxart_ether.h | 185 #define SW_RST BIT(2) /* software reset, last 64 AHB clocks */ macro
|
| /drivers/net/dsa/b53/ |
| A D | b53_regs.h | 159 #define SW_RST BIT(7) macro
|
| A D | b53_common.c | 987 reg |= SW_RST | EN_SW_RST | EN_CH_RST; in b53_switch_reset()
992 if (!(reg & SW_RST)) in b53_switch_reset()
|
| /drivers/spi/ |
| A D | spi-mtk-snfi.c | 189 #define SW_RST BIT(28) macro
418 nfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST); in mtk_snand_mac_reset()
|
Completed in 27 milliseconds