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Searched refs:TARGET (Results 1 – 22 of 22) sorted by relevance

/drivers/gpu/drm/nouveau/dispnv50/
A Dwndwca7e.c55 NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, TARGET, PHYSICAL_NVM) | in wndwca7e_image_set()
128 NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, TARGET, PHYSICAL_NVM) | in wndwca7e_ilut_set()
173 NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, TARGET, PHYSICAL_NVM) | in wndwca7e_ntfy_set()
A Dcrcca7d.c32 NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, TARGET, PHYSICAL_NVM) | in crcca7d_set_ctx()
A Dheadca7d.c148 NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, TARGET, PHYSICAL_NVM) | in headca7d_curs_set()
203 NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, TARGET, PHYSICAL_NVM) | in headca7d_olut_set()
A Dcoreca7d.c33 NVDEF(NVCA7D, SET_SURFACE_ADDRESS_LO_NOTIFIER, TARGET, PHYSICAL_NVM) | in coreca7d_update()
/drivers/gpu/drm/nouveau/
A Dnouveau_dmem.c451 NVDEF(NVA0B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB)); in nvc0b5_migrate_copy()
455 NVDEF(NVA0B5, SET_SRC_PHYS_MODE, TARGET, COHERENT_SYSMEM)); in nvc0b5_migrate_copy()
468 NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB)); in nvc0b5_migrate_copy()
472 NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM)); in nvc0b5_migrate_copy()
523 NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB)); in nvc0b5_migrate_clear()
527 NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM)); in nvc0b5_migrate_clear()
/drivers/scsi/
A Daha152x.h140 #define TARGET 0x80 macro
A D53c700.scr164 SET TARGET
166 CLEAR TARGET
A D53c700_d.h_shipped200 SET TARGET
208 CLEAR TARGET
A Daha152x.c2623 if (s & TARGET) in get_ports()
2664 if (s & TARGET) in get_ports()
/drivers/bus/
A Dmvebu-mbus.c1160 #define TARGET(id) (((id) & 0x0F000000) >> 24) macro
1204 target = TARGET(windowid); in mbus_dt_setup()
/drivers/scsi/aic7xxx/
A Daic7xxx_reg_print.c_shipped98 { "TARGET", 0x80, 0x80 }
A Daic7xxx.seq181 test SSTAT0, TARGET jz initiator_reselect;
443 test SSTAT0, TARGET jz initiator_select;
924 test SSTAT0, TARGET jnz ultra2_dma_loop;
1100 test SSTAT0, TARGET jz dma_last_sg;
1251 test SSTAT0, TARGET jnz data_phase_loop;
1263 test SSTAT0, TARGET jnz data_phase_done;
A Daic79xx_reg_print.c_shipped262 { "TARGET", 0x80, 0x80 }
A Daic7xxx_reg.h_shipped271 #define TARGET 0x80
A Daic79xx_reg.h_shipped741 #define TARGET 0x80
A Daic7xxx.reg303 field TARGET 0x80 /* Board acting as target */
A Daic79xx.reg1918 field TARGET 0x80 /* Board acting as target */
A Daic79xx.seq1738 test SSTAT0, TARGET jnz data_phase_done;
A Daic7xxx_core.c2751 if (ahc_inb(ahc, SSTAT0) & TARGET) in ahc_fetch_devinfo()
A Daic79xx_core.c4277 if (ahd_inb(ahd, SSTAT0) & TARGET) in ahd_fetch_devinfo()
/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
A Dcom.fuc268 // load dma objects back into TARGET regs
/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
A Ddisp.c977 NVVAL(NV0073_CTRL, DP_DATA, TARGET, target); in r535_dp_train_target()

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