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Searched refs:TCR (Results 1 – 20 of 20) sorted by relevance

/drivers/clocksource/
A Dtimer-keystone.c24 #define TCR 0x20 macro
79 tcr = keystone_timer_readl(TCR); in keystone_timer_config()
86 keystone_timer_writel(off, TCR); in keystone_timer_config()
102 keystone_timer_writel(tcr, TCR); in keystone_timer_config()
110 tcr = keystone_timer_readl(TCR); in keystone_timer_disable()
114 keystone_timer_writel(tcr, TCR); in keystone_timer_disable()
178 keystone_timer_writel(0, TCR); in keystone_timer_init()
A Dsh_tmu.c73 #define TCR 2 /* channel register */ macro
99 if (reg_nr == TCR) in sh_tmu_read()
121 if (reg_nr == TCR) in sh_tmu_write()
164 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); in __sh_tmu_enable()
189 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); in __sh_tmu_disable()
216 sh_tmu_read(ch, TCR); in sh_tmu_set_next()
219 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); in sh_tmu_set_next()
239 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); in sh_tmu_interrupt()
241 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); in sh_tmu_interrupt()
A Dsh_mtu2.c56 #define TCR 0 /* channel register */ macro
147 [TCR] = 0,
231 sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64); in sh_mtu2_enable()
/drivers/watchdog/
A Ddavinci_wdt.c36 #define TCR (0x20) macro
80 iowrite32(0, davinci_wdt->base + TCR); in davinci_wdt_start()
94 iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR); in davinci_wdt_start()
149 iowrite32(0, davinci_wdt->base + TCR); in davinci_wdt_restart()
/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
A Dfw.c40 cpustatus = rtl_read_byte(rtlpriv, TCR); in _rtl92s_firmware_enable_cpu()
207 cpustatus = rtl_read_byte(rtlpriv, TCR); in _rtl92s_firmware_checkready()
224 cpustatus = rtl_read_byte(rtlpriv, TCR); in _rtl92s_firmware_checkready()
247 cpustatus = rtl_read_byte(rtlpriv, TCR); in _rtl92s_firmware_checkready()
267 cpustatus = rtl_read_byte(rtlpriv, TCR); in _rtl92s_firmware_checkready()
286 tmpu4b = rtl_read_dword(rtlpriv, TCR); in _rtl92s_firmware_checkready()
287 rtl_write_dword(rtlpriv, TCR, (tmpu4b & (~TCR_ICV))); in _rtl92s_firmware_checkready()
A Dhw.c574 rtl_write_byte(rtlpriv, TCR, 0); in _rtl92se_macconfig_before_fwdownload()
714 tmpu1b = rtl_read_byte(rtlpriv, TCR); in _rtl92se_macconfig_before_fwdownload()
761 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) | in _rtl92se_macconfig_after_fwdownload()
1178 temp = rtl_read_dword(rtlpriv, TCR); in _rtl92se_set_media_status()
1179 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8))); in _rtl92se_set_media_status()
1180 rtl_write_dword(rtlpriv, TCR, temp | BIT(8)); in _rtl92se_set_media_status()
1421 rtl_write_byte(rtlpriv, TCR, 0); in _rtl92se_power_domain_init()
A Dreg.h36 #define TCR 0x0044 macro
/drivers/net/ethernet/smsc/
A Dsmc91c92_cs.c149 #define TCR 0 /* transmit control register */ macro
1101 mask_bits(0xff00, ioaddr + TCR); in smc_close()
1297 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR); in smc_tx_err()
1332 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR); in smc_eph_irq()
1656 outw(TCR_CLEAR, ioaddr + TCR); in smc_reset()
1685 TCR_ENABLE | TCR_PAD_EN | smc->duplex, ioaddr + TCR); in smc_reset()
1791 outw(inw(ioaddr + TCR) | smc->duplex, ioaddr + TCR); in media_check()
1866 tmp = inw(ioaddr + TCR); in smc_netdev_get_ecmd()
1893 tmp = inw(ioaddr + TCR); in smc_netdev_set_ecmd()
1898 outw(tmp, ioaddr + TCR); in smc_netdev_set_ecmd()
A Dsmc9194.c332 outw( TCR_CLEAR, ioaddr + TCR ); in smc_reset()
363 outw( TCR_NORMAL, ioaddr + TCR ); in smc_enable()
394 outb( TCR_CLEAR, ioaddr + TCR ); in smc_shutdown()
1286 outw( inw( ioaddr + TCR ) | TCR_ENABLE, ioaddr + TCR ); in smc_tx()
A Dsmc9194.h64 #define TCR 0 /* transmit control register */ macro
/drivers/tty/
A Dsynclink_gt.c364 #define TCR 0x82 /* tx control */ macro
1322 value = rd_reg16(info, TCR); in set_break()
1327 wr_reg16(info, TCR, value); in set_break()
2781 val = rd_reg16(info, TCR); in set_interface()
2786 wr_reg16(info, TCR, val); in set_interface()
3919 wr_reg16(info, TCR, in tx_start()
4050 wr_reg16(info, TCR, val); in async_mode()
4212 wr_reg16(info, TCR, val); in sync_mode()
4374 tcr = rd_reg16(info, TCR); in tx_set_idle()
4384 wr_reg16(info, TCR, tcr); in tx_set_idle()
[all …]
/drivers/dma/sh/
A Dshdmac.c39 #define TCR 0x08 /* Transfer Count Register */ macro
218 sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR); in dmae_set_reg()
422 (sh_dmae_readl(sh_chan, TCR) << sh_chan->xmit_shift); in sh_dmae_get_partial()
/drivers/net/ethernet/via/
A Dvia-velocity.c933 BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR); in velocity_set_media_mode()
940 BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR); in velocity_set_media_mode()
1850 BYTE_REG_BITS_ON(TCR_TB2BDIS, &regs->TCR); in velocity_error()
1852 BYTE_REG_BITS_OFF(TCR_TB2BDIS, &regs->TCR); in velocity_error()
2565 td_ptr->tdesc1.TCR = TCR0_TIC; in velocity_xmit()
2599 td_ptr->tdesc1.TCR |= TCR0_VETAG; in velocity_xmit()
2608 td_ptr->tdesc1.TCR |= TCR0_TCPCK; in velocity_xmit()
2610 td_ptr->tdesc1.TCR |= (TCR0_UDPCK); in velocity_xmit()
2611 td_ptr->tdesc1.TCR |= TCR0_IPCK; in velocity_xmit()
A Dvia-velocity.h199 u8 TCR; member
970 volatile u8 TCR; member
/drivers/net/ethernet/amd/
A Dariadne.h381 volatile u_char TCR; /* Timer Control Register */ member
/drivers/net/wan/
A Dhd64572.h103 #define TCR 0x152 /* Tx DMA Critical Request Reg */ macro
A Dhd64572.c462 sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */ in sca_open()
/drivers/net/usb/
A Drtl8150.c24 #define TCR 0x012f macro
638 set_registers(dev, TCR, 1, &tcr); in enable_net_traffic()
/drivers/spi/
A Dspi-atmel.c944 spi_writel(as, TCR, len); in atmel_spi_pdc_next_xfer()
1427 spi_readl(as, TCR), spi_readl(as, RCR)); in atmel_spi_one_transfer()
1436 spi_writel(as, TCR, 0); in atmel_spi_one_transfer()
/drivers/net/ethernet/cadence/
A Dmacb_main.c4641 macb_writel(lp, TCR, skb->len); in at91ether_start_xmit()

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