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Searched refs:THERM_INTH_MASK (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/radeon/
A Dtrinityd.h213 # define THERM_INTH_MASK (1 << 24) macro
A Dcikd.h305 #define THERM_INTH_MASK (1 << 24) macro
A Dkv_dpm.c1020 thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK; in kv_enable_thermal_int()
1022 thermal_int &= ~(THERM_INTH_MASK | THERM_INTL_MASK); in kv_enable_thermal_int()
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0.c879 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1); in smu_v14_0_set_irq_state()
906 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); in smu_v14_0_set_irq_state()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dsmu_v11_0.c1343 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1); in smu_v11_0_set_irq_state()
1365 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); in smu_v11_0_set_irq_state()
/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0.c1201 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1); in smu_v13_0_set_irq_state()
1223 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); in smu_v13_0_set_irq_state()

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