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Searched refs:TO_DCN_DCCG (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
A Ddcn35_dccg.c30 #define TO_DCN_DCCG(dccg)\ macro
138 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_dsc_clk_rcg()
167 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_symclk32_se_rcg()
206 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_symclk32_le_rcg()
233 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_physymclk_rcg()
270 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_symclk_fe_rcg()
318 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_symclk_be_rcg()
364 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_dtbclk_p_rcg()
392 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_dppclk_rcg()
424 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg35_set_dpstreamclk_rcg()
[all …]
/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
A Ddcn20_dccg.c32 #define TO_DCN_DCCG(dccg)\ macro
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_update_dpp_dto()
81 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_get_dccg_ref_freq()
102 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_set_fifo_errdet_ovr_en()
111 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_otg_add_pixel()
123 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_otg_drop_pixel()
172 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(*dccg); in dcn_dccg_destroy()
/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
A Ddcn31_dccg.c31 #define TO_DCN_DCCG(dccg)\ macro
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_update_dpp_dto()
99 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_enable_dpstreamclk()
131 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_disable_dpstreamclk()
178 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_enable_symclk32_se()
230 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_disable_symclk32_se()
281 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_enable_symclk32_le()
307 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_disable_symclk32_le()
332 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_set_symclk32_le_root_clock_gating()
356 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_disable_dscclk()
[all …]
/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
A Ddcn401_dccg.c40 #define TO_DCN_DCCG(dccg)\ macro
58 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dcn401_set_dppclk_enable()
79 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_update_dpp_dto()
111 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_wait_for_dentist_change_done()
125 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_get_pixel_rate_div()
163 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_set_pixel_rate_div()
217 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_set_dtbclk_p_src()
273 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_set_physymclk()
366 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_otg_add_pixel()
375 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg401_otg_drop_pixel()
[all …]
/drivers/gpu/drm/amd/display/dc/dccg/dcn32/
A Ddcn32_dccg.c30 #define TO_DCN_DCCG(dccg)\ macro
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_trigger_dio_fifo_resync()
64 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_get_pixel_rate_div()
106 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_set_pixel_rate_div()
153 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_set_dtbclk_p_src()
208 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_set_dtbclk_dto()
281 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_set_dpstreamclk()
315 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_otg_add_pixel()
324 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_otg_drop_pixel()
/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
A Ddcn314_dccg.c33 #define TO_DCN_DCCG(dccg)\ macro
51 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_trigger_dio_fifo_resync()
64 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_get_pixel_rate_div()
106 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_set_pixel_rate_div()
153 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_set_dtbclk_p_src()
209 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_set_dtbclk_dto()
255 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_set_dpstreamclk()
334 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_dpp_root_clock_control()
/drivers/gpu/drm/amd/display/dc/dccg/dcn21/
A Ddcn21_dccg.c31 #define TO_DCN_DCCG(dccg)\ macro
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_update_dpp_dto()
/drivers/gpu/drm/amd/display/dc/dccg/dcn301/
A Ddcn301_dccg.c30 #define TO_DCN_DCCG(dccg)\ macro
/drivers/gpu/drm/amd/display/dc/dccg/dcn201/
A Ddcn201_dccg.c31 #define TO_DCN_DCCG(dccg)\ macro
/drivers/gpu/drm/amd/display/dc/dccg/dcn30/
A Ddcn30_dccg.c30 #define TO_DCN_DCCG(dccg)\ macro

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