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Searched refs:ULONG (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/include/
A Datombios.h44 #ifndef ULONG
605 ULONG ulClock;
632 ULONG ulReserved;
656 ULONG ulReserved;
666 ULONG ulReserved;
5479 ULONG ulSM_A0;
5480 ULONG ulSM_A1;
5481 ULONG ulSM_A2;
5482 ULONG ulSM_A3;
5483 ULONG ulSM_A4;
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A Dpptable.h333 ULONG ulVCLK;
334 ULONG ulDCLK;
379 ULONG ulFlags;
448 ULONG rsv2[2];
457 ULONG rsv2[2];
731 ULONG ulApuTDP;
734 ULONG ulTjmax;
741 ULONG ulDeviceID;
745 ULONG ulDClk;
746 ULONG ulEClk;
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A Datom-types.h31 typedef uint32_t ULONG; typedef
/drivers/gpu/drm/radeon/
A Datombios.h45 #ifndef ULONG
569 ULONG ulReserved[2];
575 ULONG ulMemoryClock;
576 ULONG ulReserved;
4701 ULONG ulMaxVddc;
4702 ULONG ulMinVddc;
4818 ULONG ulIdleNClk;
7336 ULONG ulRegVal;
7342 ULONG ulRegVal;
7919 ULONG Signature;
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A Dpptable.h303 ULONG ulCapsAndSettings;
306 ULONG ulVCLK;
307 ULONG ulDCLK;
352 ULONG ulFlags;
421 ULONG rsv2[2];
678 ULONG ulPlatformTDP;
680 ULONG ulPlatformTDC;
682 ULONG ulApuTDP;
683 ULONG ulDGpuTDP;
684 ULONG ulDGpuUlvPower;
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A Datom-types.h31 typedef uint32_t ULONG; typedef
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dpptable_v1_0.h106 ULONG ulGoldenPPID;
175 ULONG ulMclk;
188 ULONG ulSclk;
203 ULONG ulSclk;
207 ULONG ulSclkOffset;
232 ULONG ulPCIE_Sclk;
467 ULONG ulApuTDP;
468 ULONG ulDGpuTDP;
470 ULONG ulTjmax;
474 ULONG ulSCLKLimit;
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A Dvega20_pptable.h78 ULONG ODFeatureCount;
80 ULONG ODSettingCount;
81 ULONG ODSettingsMax[ATOM_VEGA20_ODSETTING_MAX_COUNT]; //Upper Limit for each OD Setting
82 ULONG ODSettingsMin[ATOM_VEGA20_ODSETTING_MAX_COUNT]; //Lower Limit for each OD Setting
103 ULONG PowerSavingClockCount; // Count of PowerSavingClock Mode
104 …ULONG PowerSavingClockMax[ATOM_VEGA20_PPCLOCK_MAX_COUNT]; // PowerSavingClock Mode Clock Maxi…
105 …ULONG PowerSavingClockMin[ATOM_VEGA20_PPCLOCK_MAX_COUNT]; // PowerSavingClock Mode Clock Mini…
112 ULONG ulGoldenPPID;
113 ULONG ulGoldenRevision;
116 ULONG ulPlatformCaps;
A Dvega10_pptable.h77 ULONG ulGoldenPPID; /* PPGen use only */
78 ULONG ulGoldenRevision; /* PPGen use only */
81 ULONG ulMaxODEngineClock; /* For Overdrive. */
82 ULONG ulMaxODMemoryClock; /* For Overdrive. */
125 ULONG ulCapsAndSettings;
148 ULONG ulClk;
414 ULONG ulBoostClock;
415 ULONG Reserved[2];
419 ULONG ulSOCCLKLimit;
420 ULONG ulGFXCLKLimit;
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A Dvega12_pptable.h79 ULONG ulGoldenPPID;
80 ULONG ulGoldenRevision;
83 ULONG ulPlatformCaps;
94 ULONG PowerSavingClockMax[ATOM_VEGA12_PPCLOCK_COUNT];
95 ULONG PowerSavingClockMin[ATOM_VEGA12_PPCLOCK_COUNT];
97 ULONG ODSettingsMax[ATOM_VEGA12_ODSETTING_COUNT];
98 ULONG ODSettingsMin[ATOM_VEGA12_ODSETTING_COUNT];
A Dprocesspptables.c766 static ULONG size_of_entry_v2(ULONG num_dpm_levels) in size_of_entry_v2()
774 ULONG entry_index) in get_state_entry_v2()
776 ULONG i; in get_state_entry_v2()
1495 cac_leakage_table->count = (ULONG)table->ucNumEntries; in get_cac_leakage_table()
A Dppatomctrl.h289 ULONG DIDT_REG[24];
A Dvega10_hwmgr.c93 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Dfiji_smumgr.c1500 ULONG trrds, trrdl; in fiji_populate_memory_timing_parameters()

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