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Searched refs:V3D_WRITE (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/vc4/
A Dvc4_irq.c107 V3D_WRITE(V3D_BPOS, bo->base.base.size); in vc4_overflow_mem_work()
108 V3D_WRITE(V3D_INTCTL, V3D_INT_OUTOMEM); in vc4_overflow_mem_work()
109 V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM); in vc4_overflow_mem_work()
218 V3D_WRITE(V3D_INTCTL, intctl); in vc4_irq()
222 V3D_WRITE(V3D_INTDIS, V3D_INT_OUTOMEM); in vc4_irq()
258 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS); in vc4_irq_prepare()
275 V3D_WRITE(V3D_INTENA, V3D_INT_FLDONE | V3D_INT_FRDONE); in vc4_irq_enable()
290 V3D_WRITE(V3D_INTDIS, V3D_DRIVER_IRQS); in vc4_irq_disable()
293 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS); in vc4_irq_disable()
344 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS); in vc4_irq_reset()
[all …]
A Dvc4_v3d.c170 V3D_WRITE(V3D_VPMBASE, 0); in vc4_v3d_init_hw()
303 V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM); in bin_bo_alloc()
471 V3D_WRITE(V3D_BPOA, 0); in vc4_v3d_bind()
472 V3D_WRITE(V3D_BPOS, 0); in vc4_v3d_bind()
503 V3D_WRITE(V3D_BPOA, 0); in vc4_v3d_unbind()
504 V3D_WRITE(V3D_BPOS, 0); in vc4_v3d_unbind()
A Dvc4_perfmon.c59 V3D_WRITE(V3D_PCTRS(i), perfmon->events[i]); in vc4_perfmon_start()
62 V3D_WRITE(V3D_PCTRC, mask); in vc4_perfmon_start()
63 V3D_WRITE(V3D_PCTRE, V3D_PCTRE_EN | mask); in vc4_perfmon_start()
84 V3D_WRITE(V3D_PCTRE, 0); in vc4_perfmon_stop()
A Dvc4_gem.c380 V3D_WRITE(V3D_CTNCA(thread), start); in submit_cl()
381 V3D_WRITE(V3D_CTNEA(thread), end); in submit_cl()
444 V3D_WRITE(V3D_L2CACTL, in vc4_flush_caches()
447 V3D_WRITE(V3D_SLCACTL, in vc4_flush_caches()
459 V3D_WRITE(V3D_L2CACTL, in vc4_flush_texture_caches()
462 V3D_WRITE(V3D_SLCACTL, in vc4_flush_texture_caches()
A Dvc4_drv.h645 #define V3D_WRITE(offset, val) \ macro
/drivers/gpu/drm/v3d/
A Dv3d_mmu.c42 V3D_WRITE(V3D_MMUC_CONTROL, V3D_MMUC_CONTROL_FLUSH | in v3d_mmu_flush_all()
52 V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL) | in v3d_mmu_flush_all()
65 V3D_WRITE(V3D_MMU_PT_PA_BASE, v3d->pt_paddr >> V3D_MMU_PAGE_SHIFT); in v3d_mmu_set_page_table()
66 V3D_WRITE(V3D_MMU_CTL, in v3d_mmu_set_page_table()
75 V3D_WRITE(V3D_MMU_ILLEGAL_ADDR, in v3d_mmu_set_page_table()
78 V3D_WRITE(V3D_MMUC_CONTROL, V3D_MMUC_CONTROL_ENABLE); in v3d_mmu_set_page_table()
A Dv3d_irq.c168 V3D_WRITE(V3D_HUB_INT_CLR, intsts); in v3d_hub_irq()
215 V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL)); in v3d_hub_irq()
272 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver)); in v3d_irq_init()
331 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS(v3d->ver)); in v3d_irq_enable()
332 V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS(v3d->ver)); in v3d_irq_enable()
343 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0); in v3d_irq_disable()
354 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver)); in v3d_irq_disable()
A Dv3d_sched.c359 V3D_WRITE(V3D_TFU_IIA(v3d->ver), job->args.iia); in v3d_tfu_job_run()
360 V3D_WRITE(V3D_TFU_IIS(v3d->ver), job->args.iis); in v3d_tfu_job_run()
361 V3D_WRITE(V3D_TFU_ICA(v3d->ver), job->args.ica); in v3d_tfu_job_run()
362 V3D_WRITE(V3D_TFU_IUA(v3d->ver), job->args.iua); in v3d_tfu_job_run()
363 V3D_WRITE(V3D_TFU_IOA(v3d->ver), job->args.ioa); in v3d_tfu_job_run()
365 V3D_WRITE(V3D_V7_TFU_IOC, job->args.v71.ioc); in v3d_tfu_job_run()
366 V3D_WRITE(V3D_TFU_IOS(v3d->ver), job->args.ios); in v3d_tfu_job_run()
367 V3D_WRITE(V3D_TFU_COEF0(v3d->ver), job->args.coef[0]); in v3d_tfu_job_run()
369 V3D_WRITE(V3D_TFU_COEF1(v3d->ver), job->args.coef[1]); in v3d_tfu_job_run()
370 V3D_WRITE(V3D_TFU_COEF2(v3d->ver), job->args.coef[2]); in v3d_tfu_job_run()
[all …]
A Dv3d_gem.c86 V3D_WRITE(V3D_HUB_AXICFG, V3D_HUB_AXICFG_MAX_LEN_MASK); in v3d_reset_by_bridge()
A Dv3d_drv.h272 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) macro

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