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Searched refs:VAL (Results 1 – 25 of 27) sorted by relevance

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/drivers/net/ethernet/qlogic/qlcnic/
A Dqlcnic_hdr.h641 #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4))) argument
642 #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4))) argument
643 #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4))) argument
644 #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4))) argument
645 #define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) &= ~(3 << (FN * 4))) argument
647 #define QLC_DEV_GET_DRV(VAL, FN) (0xf & ((VAL) >> (FN * 4))) argument
648 #define QLC_DEV_SET_DRV(VAL, FN) ((VAL) << (FN * 4)) argument
678 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) argument
A Dqlcnic_83xx_hw.h405 #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2))) argument
406 #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2)) argument
A Dqlcnic.h880 #define QLCNIC_IS_LB_CONFIGURED(VAL) \ argument
881 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
/drivers/watchdog/
A Dit87_wdt.c44 #define VAL 0x2f macro
136 outb(0x02, VAL); in superio_exit()
143 outb(ldn, VAL); in superio_select()
149 return inb(VAL); in superio_inb()
155 outb(val, VAL); in superio_outb()
163 val = inb(VAL) << 8; in superio_inw()
165 val |= inb(VAL); in superio_inw()
A Dit8712f_wdt.c57 #define VAL 0x2f /* The value to read/write */ macro
95 return inb(VAL); in superio_inb()
101 outb(val, VAL); in superio_outb()
108 val = inb(VAL) << 8; in superio_inw()
110 val |= inb(VAL); in superio_inw()
117 outb(ldn, VAL); in superio_select()
138 outb(0x02, VAL); in superio_exit()
/drivers/net/ethernet/qlogic/netxen/
A Dnetxen_nic_hdr.h950 #define NETXEN_DIMM_MEMTYPE(VAL) ((VAL >> 3) & 0xf) argument
951 #define NETXEN_DIMM_NUMROWS(VAL) ((VAL >> 7) & 0xf) argument
952 #define NETXEN_DIMM_NUMCOLS(VAL) ((VAL >> 11) & 0xf) argument
953 #define NETXEN_DIMM_NUMRANKS(VAL) ((VAL >> 15) & 0x3) argument
954 #define NETXEN_DIMM_DATAWIDTH(VAL) ((VAL >> 18) & 0x3) argument
955 #define NETXEN_DIMM_NUMBANKS(VAL) ((VAL >> 21) & 0xf) argument
956 #define NETXEN_DIMM_TYPE(VAL) ((VAL >> 25) & 0x3f) argument
991 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) argument
/drivers/gpio/
A Dgpio-it87.c38 #define VAL 0x2f macro
95 outb(0x02, VAL); in superio_exit()
102 outb(ldn, VAL); in superio_select()
108 return inb(VAL); in superio_inb()
114 outb(val, VAL); in superio_outb()
122 val = inb(VAL) << 8; in superio_inw()
124 val |= inb(VAL); in superio_inw()
/drivers/staging/rtl8723bs/hal/
A DHalPhyRf_8723B.c18 #define VAL 1 macro
960 …pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_X… in _PHY_PathAFillIQKMatrix8723B()
968 …pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_E… in _PHY_PathAFillIQKMatrix8723B()
976 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100; in _PHY_PathAFillIQKMatrix8723B()
992 …pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_R… in _PHY_PathAFillIQKMatrix8723B()
1038 …pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_X… in _PHY_PathBFillIQKMatrix8723B()
1051 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100; in _PHY_PathBFillIQKMatrix8723B()
1083 (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) && in ODM_SetIQCbyRFpath()
1084 (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0) && in ODM_SetIQCbyRFpath()
1085 (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && in ODM_SetIQCbyRFpath()
[all …]
/drivers/scsi/
A Dsun3x_esp.c45 #define dma_write32(VAL, REG) \
46 writel((VAL), esp->dma_regs + (REG))
50 #define dma_write32(VAL, REG) \ argument
51 do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)
A Daha152x.h289 #define SETPORT(PORT, VAL) outb( (VAL), (PORT) ) argument
A Dmac_esp.c50 #define esp_write8(VAL, REG) mac_esp_write8(esp, VAL, REG) argument
A Dsun_esp.c34 #define dma_write32(VAL, REG) \ argument
35 sbus_writel((VAL), esp->dma_regs + (REG))
/drivers/comedi/drivers/
A Ds626.h447 #define S626_I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24)) argument
448 #define S626_I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16)) argument
449 #define S626_I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8)) argument
/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/
A Dmsgfn.h12 # define E(RPC, VAL) NV_VGPU_MSG_EVENT_##RPC = VAL, argument
A Drpcfn.h12 # define X(UNIT, RPC, VAL) NV_VGPU_MSG_FUNCTION_##RPC = VAL, argument
/drivers/hwmon/
A Dsmsc47b397.c42 #define VAL 0x2f /* The value to read/write */ macro
47 outb(val, VAL); in superio_outb()
53 return inb(VAL); in superio_inb()
A Dsmsc47m1.c44 #define VAL 0x2f /* The value to read/write */ macro
50 outb(val, VAL); in superio_outb()
57 return inb(VAL); in superio_inb()
/drivers/net/ethernet/freescale/fs_enet/
A Dmii-fec.c46 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) argument
A Dmac-fcc.c68 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) argument
/drivers/scsi/qla4xxx/
A Dql4_nx.h746 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0) argument
747 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) argument
/drivers/scsi/qla2xxx/
A Dqla_nx.h708 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0) argument
709 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) argument
/drivers/gpu/drm/panel/
A Dpanel-novatek-nt39016.c70 #define RV(REG, VAL) { .reg = (REG), .def = (VAL), .delay_us = 2 } argument
/drivers/accel/ivpu/
A Divpu_mmu.c441 return REGV_POLL_FLD(IVPU_MMU_REG_CR0ACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US); in ivpu_mmu_reg_write_cr0()
448 return REGV_POLL_FLD(IVPU_MMU_REG_IRQ_CTRLACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US); in ivpu_mmu_reg_write_irq_ctrl()
468 ret = REGV_POLL_FLD(IVPU_MMU_REG_CMDQ_CONS, VAL, cmdq->prod, in ivpu_mmu_cmdq_wait_for_cons()
883 return REGV_POLL_FLD(IVPU_MMU_REG_CR0ACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US); in ivpu_mmu_evtq_set()
/drivers/pinctrl/
A Dpinctrl-rockchip.c236 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ argument
242 .route_val = VAL, \
246 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \ argument
247 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
249 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \ argument
250 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
252 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \ argument
253 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
/drivers/net/ethernet/huawei/hinic/
A Dhinic_hw_cmdq.c625 errcode = CMDQ_WQE_ERRCODE_GET(be32_to_cpu(status->status_info), VAL); in cmdq_cmd_ceq_handler()

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