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Searched refs:VALID (Results 1 – 25 of 26) sorted by relevance

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/drivers/sh/intc/
A Dchip.c157 #define VALID(x) (x | SENSE_VALID_FLAG) macro
160 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
161 [IRQ_TYPE_EDGE_RISING] = VALID(1),
162 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
167 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
170 [IRQ_TYPE_EDGE_BOTH] = VALID(4),
/drivers/gpu/drm/i915/selftests/
A Di915_vma.c265 VALID(0, PIN_GLOBAL), in igt_vma_pin1()
266 VALID(0, PIN_GLOBAL | PIN_MAPPABLE), in igt_vma_pin1()
268 VALID(0, PIN_GLOBAL | PIN_OFFSET_BIAS | 4096), in igt_vma_pin1()
269 VALID(0, PIN_GLOBAL | PIN_OFFSET_BIAS | 8192), in igt_vma_pin1()
280 VALID(4096, PIN_GLOBAL), in igt_vma_pin1()
281 VALID(8192, PIN_GLOBAL), in igt_vma_pin1()
282 VALID(ggtt->mappable_end - 4096, PIN_GLOBAL | PIN_MAPPABLE), in igt_vma_pin1()
283 VALID(ggtt->mappable_end, PIN_GLOBAL | PIN_MAPPABLE), in igt_vma_pin1()
285 VALID(ggtt->vm.total - 4096, PIN_GLOBAL), in igt_vma_pin1()
286 VALID(ggtt->vm.total, PIN_GLOBAL), in igt_vma_pin1()
[all …]
/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
A Dhw_atl2_internal.h87 #define HW_ATL2_ACTION(ACTION, RSS, INDEX, VALID) \ argument
91 (((VALID) & 0x1U) << 0))
/drivers/gpu/drm/imagination/
A Dpvr_mmu.c434 return PVR_PAGE_TABLE_FIELD_GET(2, PC, VALID, entry); in pvr_page_table_l2_entry_raw_is_valid()
454 PVR_PAGE_TABLE_FIELD_PREP(2, PC, VALID, true) | in pvr_page_table_l2_entry_raw_set()
557 return PVR_PAGE_TABLE_FIELD_GET(1, PD, VALID, entry); in pvr_page_table_l1_entry_raw_is_valid()
575 PVR_PAGE_TABLE_FIELD_PREP(1, PD, VALID, true) | in pvr_page_table_l1_entry_raw_set()
717 return PVR_PAGE_TABLE_FIELD_GET(0, PT, VALID, entry); in pvr_page_table_l0_entry_raw_is_valid()
739 WRITE_ONCE(entry->val, PVR_PAGE_TABLE_FIELD_PREP(0, PT, VALID, true) | in pvr_page_table_l0_entry_raw_set()
/drivers/net/ethernet/huawei/hinic/
A Dhinic_debugfs.c74 VALID, enumerator
114 case VALID: in hinic_dbg_get_func_table()
A Dhinic_port.c722 ctx |= HINIC_RSS_TYPE_SET(1, VALID) | in hinic_set_rss_type()
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_amdkfd_gfx_v10.c935 VALID, in kgd_gfx_v10_set_address_watch()
943 VALID, in kgd_gfx_v10_set_address_watch()
967 VALID, in kgd_gfx_v10_set_address_watch()
975 VALID, in kgd_gfx_v10_set_address_watch()
A Damdgpu_amdkfd_aldebaran.c152 VALID, in kgd_gfx_aldebaran_set_address_watch()
A Damdgpu_amdkfd_gfx_v12.c344 VALID, in kgd_gfx_v12_set_address_watch()
A Damdgpu_amdkfd_gfx_v9.c851 VALID, in kgd_gfx_v9_set_address_watch()
869 VALID, in kgd_gfx_v9_set_address_watch()
A Damdgpu_amdkfd_gc_9_4_3.c490 VALID, in kgd_gfx_v9_4_3_set_address_watch()
A Damdgpu_amdkfd_gfx_v11.c769 VALID, in kgd_gfx_v11_set_address_watch()
/drivers/thermal/qcom/
A Dtsens-v1.c136 REG_FIELD_FOR_EACH_SENSOR11(VALID, TM_Sn_STATUS_OFF, 14, 14),
A Dtsens-v2.c129 REG_FIELD_FOR_EACH_SENSOR16(VALID, TM_Sn_STATUS_OFF, 21, 21),
/drivers/usb/renesas_usbhs/
A Dcommon.h162 #define VALID (1 << 3) /* USB Request Receive */ macro
/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
A Dvmmgh100.c272 map->type |= NVDEF(NV_MMU, VER3_PTE, VALID, TRUE); in gh100_vmm_valid()
/drivers/net/wireless/intel/iwlwifi/dvm/
A Deeprom.c387 TXP_CHECK_AND_PRINT(VALID), in iwl_eeprom_enhanced_txpower()
574 CHECK_AND_PRINT_I(VALID), in iwl_init_channel_map()
/drivers/net/ethernet/amd/xgbe/
A Dxgbe-pci.c249 if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID) || in xgbe_pci_probe()
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0.c922 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); in smu_v14_0_set_irq_state()
931 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); in smu_v14_0_set_irq_state()
/drivers/accel/ivpu/
A Divpu_hw_btrs.c138 if (!REG_TEST_FLD(VPU_HW_BTRS_LNL_TILE_FUSE, VALID, fuse)) { in read_tile_config_fuse()
/drivers/net/wireless/intel/iwlwifi/
A Diwl-nvm-parse.c325 CHECK_AND_PRINT_I(VALID), in iwl_nvm_print_channel_flags()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dsmu_v11_0.c1380 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); in smu_v11_0_set_irq_state()
/drivers/usb/gadget/udc/
A Dr8a66597-udc.c1292 r8a66597_write(r8a66597, ~VALID, INTSTS0); in setup_packet()
/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0.c1238 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); in smu_v13_0_set_irq_state()
A Dsmu_v13_0_6_ppt.c1857 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); in smu_v13_0_6_set_irq_state()

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