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Searched refs:VCLK_SRC_SEL_MASK (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dsid.h64 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
A Dsi.c1798 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in si_set_uvd_clocks()
1874 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in si_set_uvd_clocks()
/drivers/gpu/drm/radeon/
A Drv770.c66 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in rv770_set_uvd_clocks()
132 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in rv770_set_uvd_clocks()
A Drv770d.h58 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
A Dsid.h142 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
A Devergreend.h363 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
A Dr600d.h1577 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
A Dr600.c211 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in r600_set_uvd_clocks()
289 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in r600_set_uvd_clocks()
A Devergreen.c1198 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in evergreen_set_uvd_clocks()
1271 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in evergreen_set_uvd_clocks()
A Dsi.c6983 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in si_set_uvd_clocks()
7057 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in si_set_uvd_clocks()
/drivers/video/fbdev/aty/
A Dradeon_base.c1378 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); in radeon_write_pll_regs()
1438 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); in radeon_write_pll_regs()

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