Searched refs:VEBOX_RING_BASE (Results 1 – 9 of 9) sorted by relevance
| /drivers/gpu/drm/i915/gt/ |
| A D | intel_engine_regs.h | 44 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
45 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
46 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
|
| A D | intel_rc6.c | 463 (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) { in bxt_check_bios_rc6_setup()
|
| A D | intel_engine_cs.c | 198 { .graphics_ver = 7, .base = VEBOX_RING_BASE }
|
| /drivers/gpu/drm/xe/regs/ |
| A D | xe_engine_regs.h | 27 #define VEBOX_RING_BASE 0x1c8000 macro
|
| /drivers/gpu/drm/i915/gvt/ |
| A D | mmio_context.c | 143 {VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
|
| A D | handlers.c | 2185 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
2814 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
|
| /drivers/gpu/drm/i915/ |
| A D | intel_gvt_mmio_table.c | 54 MMIO_F(prefix(VEBOX_RING_BASE), s); \
1259 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40); in iterate_bxt_mmio()
|
| A D | i915_reg.h | 255 #define VEBOX_RING_BASE 0x1a000 macro
|
| /drivers/gpu/drm/xe/ |
| A D | xe_hw_engine.c | 209 .mmio_base = VEBOX_RING_BASE,
|
Completed in 32 milliseconds