Searched refs:VECS0 (Results 1 – 17 of 17) sorted by relevance
| /drivers/gpu/drm/i915/ |
| A D | i915_pci.c | 447 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
498 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
560 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
581 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
614 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
643 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
650 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
667 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
677 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
685 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
[all …]
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| A D | i915_gpu_error.c | 1303 case VECS0: in engine_record_registers()
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| /drivers/gpu/drm/i915/gvt/ |
| A D | mmio_context.c | 143 {VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
171 [VECS0] = 0xcb00,
358 [VECS0] = 0x4270,
415 [VECS0] = 0xcb00, in switch_mocs()
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| A D | execlist.c | 53 [VECS0] = VECS_AS_CONTEXT_SWITCH,
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| A D | cmd_parser.c | 433 #define R_VECS BIT(VECS0)
633 [VECS0] = {
1175 [VECS0] = {
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| A D | handlers.c | 352 engine_mask |= BIT(VECS0); in gdrst_mmio_write()
2116 id = VECS0; in gvt_reg_tlb_control_handler()
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| /drivers/gpu/drm/i915/gt/ |
| A D | intel_engine_types.h | 132 VECS0, enumerator
136 #define _VECS(n) (VECS0 + (n))
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| A D | intel_engine_user.c | 168 [VIDEO_ENHANCEMENT_CLASS] = { VECS0, I915_MAX_VECS }, in legacy_ring_idx()
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| A D | intel_engine.h | 101 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
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| A D | intel_engine_cs.c | 193 [VECS0] = {
420 [VECS0] = GEN11_GRDOM_VECS, in get_reset_domain()
439 [VECS0] = GEN6_GRDOM_VECS, in get_reset_domain()
1713 [VECS0] = MSG_IDLE_VECS0, in __cs_pending_mi_force_wakes()
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| A D | intel_mocs.c | 572 [VECS0] = __GEN9_VECS0_MOCS0, in mocs_offset()
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| A D | gen8_engine_cs.c | 179 case VECS0: in gen12_get_aux_inv_reg()
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| A D | intel_gt_irq.c | 548 if (HAS_ENGINE(gt, VECS0)) { in gen5_gt_irq_postinstall()
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| A D | intel_ring_submission.c | 103 case VECS0: in set_hwsp()
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| A D | intel_rps.c | 1944 intel_engine_cs_irq(gt->engine[VECS0], pm_iir >> 10); in gen6_rps_irq_handler()
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| A D | intel_execlists_submission.c | 3497 [VECS0] = GEN8_VECS_IRQ_SHIFT, in logical_ring_default_irqs()
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| /drivers/gpu/drm/i915/gem/ |
| A D | i915_gem_execbuffer.c | 2475 [I915_EXEC_VEBOX] = VECS0
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Completed in 83 milliseconds