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Searched refs:VMID (Results 1 – 25 of 38) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
A Ddcn20_hubp.h116 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh)
204 type VMID
/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_amdkfd_gfx_v7.c51 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); in lock_srbm()
561 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in read_vmid_from_vmfault_reg()
A Dvid.h72 #define VMID(x) ((x) << 4) macro
A Dgfx_v11_0.c2500 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache()
2544 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache()
2619 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache_rs64()
2741 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache_rs64()
2859 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64()
2865 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64()
3230 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3448 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
4088 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); in gfx_v11_0_gfx_mqd_init()
4095 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); in gfx_v11_0_gfx_mqd_init()
[all …]
A Dcikd.h65 #define VMID(x) ((x) << 4) macro
A Damdgpu_amdkfd_gfx_v10.c907 VMID, in kgd_gfx_v10_set_address_watch()
921 VMID, in kgd_gfx_v10_set_address_watch()
A Dmes_v11_0.c1111 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in mes_v11_0_mqd_init()
1187 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); in mes_v11_0_queue_init_register()
1202 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); in mes_v11_0_queue_init_register()
A Dmes_v12_0.c1193 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in mes_v12_0_mqd_init()
1276 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); in mes_v12_0_queue_init_register()
1291 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); in mes_v12_0_queue_init_register()
A Dsoc24.c107 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); in soc24_grbm_select()
A Dgfx_v12_0.c2411 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2465 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2555 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2610 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
2865 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_compute_load_microcode_rs64()
2871 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v12_0_cp_compute_load_microcode_rs64()
2982 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); in gfx_v12_0_gfx_mqd_init()
2989 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); in gfx_v12_0_gfx_mqd_init()
3162 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v12_0_compute_mqd_init()
A Dgmc_v7_0.c770 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v7_0_vm_decode_fault()
1289 VMID); in gmc_v7_0_process_interrupt()
A Dumsch_mm_v4_0.c84 data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, VMID, 0); in umsch_mm_v4_0_load_microcode()
A Damdgpu_amdkfd_gfx_v8.c45 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); in lock_srbm()
A Dgmc_v8_0.c1002 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v8_0_vm_decode_fault()
1475 VMID); in gmc_v8_0_process_interrupt()
A Dsoc21.c238 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); in soc21_grbm_select()
A Dnv.c323 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); in nv_grbm_select()
A Dgmc_v6_0.c614 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v6_0_vm_decode_fault()
/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
A Ddcn21_hubp.h91 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
/drivers/gpu/drm/radeon/
A Dcik_sdma.c961 radeon_ring_write(ring, VMID(vm_id)); in cik_dma_vm_flush()
981 radeon_ring_write(ring, VMID(0)); in cik_dma_vm_flush()
/drivers/gpu/drm/amd/display/dc/hubp/dcn31/
A Ddcn31_hubp.h224 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
A Ddcn30_hubp.c82 VMID, address->vmid); in hubp3_program_surface_flip_and_addr()
A Ddcn30_hubp.h239 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
A Ddcn401_hubp.h211 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Dsmu8_smumgr.c200 tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in smu8_load_mec_firmware()
/drivers/iommu/
A Dmsm_iommu_hw-8xxx.h191 #define SET_VMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID, v)
309 #define GET_VMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID)
919 #define VMID (VMID_MASK << VMID_SHIFT) macro

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