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Searched refs:WM_A (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c294 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { in dcn30_fpu_update_soc_for_wm_a()
516 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn30_fpu_calculate_wm_and_dlg()
669 base->bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn3_fpu_build_wm_range_table()
670 base->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn3_fpu_build_wm_range_table()
671 base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn3_fpu_build_wm_range_table()
672 …base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_ex… in dcn3_fpu_build_wm_range_table()
673 base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn3_fpu_build_wm_range_table()
674 base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0; in dcn3_fpu_build_wm_range_table()
675 base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn3_fpu_build_wm_range_table()
676 base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn3_fpu_build_wm_range_table()
[all …]
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddcn31_fpu.c458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
459 …oc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; in dcn31_update_soc_for_wm_a()
460 …soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit… in dcn31_update_soc_for_wm_a()
461 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()
474 …oc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; in dcn315_update_soc_for_wm_a()
476 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; in dcn315_update_soc_for_wm_a()
478 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; in dcn315_update_soc_for_wm_a()
/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c221 .wm_inst = WM_A,
258 .wm_inst = WM_A,
448 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn301_fpu_calculate_wm_and_dlg()
/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c211 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn32_build_wm_range_table_fpu()
212 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn32_build_wm_range_table_fpu()
214 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
217 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
218 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn32_build_wm_range_table_fpu()
219 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn32_build_wm_range_table_fpu()
220 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn32_build_wm_range_table_fpu()
2347 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()
2385 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()
2626 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
A Ddcn316_clk_mgr.c273 .wm_inst = WM_A,
310 .wm_inst = WM_A,
396 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn316_build_watermark_ranges()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
A Ddcn315_clk_mgr.c308 .wm_inst = WM_A,
345 .wm_inst = WM_A,
431 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn315_build_watermark_ranges()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_clk_mgr.c347 .wm_inst = WM_A,
384 .wm_inst = WM_A,
470 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn31_build_watermark_ranges()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.c189 clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn401_build_wm_range_table()
190 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn401_build_wm_range_table()
191 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; in dcn401_build_wm_range_table()
192 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn401_build_wm_range_table()
193 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn401_build_wm_range_table()
194 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn401_build_wm_range_table()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
A Ddcn314_clk_mgr.c406 .wm_inst = WM_A,
443 .wm_inst = WM_A,
534 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn314_build_watermark_ranges()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h34 #define WM_A 0 macro
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c43 #define WM_A 0 macro
1392 ranges.reader_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
1397 ranges.writer_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
1404 ranges.reader_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
1409 ranges.writer_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c771 .wm_inst = WM_A,
808 .wm_inst = WM_A,
845 .wm_inst = WM_A,
882 .wm_inst = WM_A,
919 .wm_inst = WM_A,
956 .wm_inst = WM_A,
2314 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn21_calculate_wm()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_clk_mgr.c649 .wm_inst = WM_A,
686 .wm_inst = WM_A,
795 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn35_build_watermark_ranges()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr.c504 ranges->writer_wm_sets[0].wm_inst = WM_A; in build_watermark_ranges()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.c434 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in vg_build_watermark_ranges()

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