Searched refs:WM_D (Results 1 – 11 of 11) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | dcn30_fpu.c | 710 base->bw_params->wm_table.nv_entries[WM_D].valid = true; in dcn3_fpu_build_wm_range_table()
711 base->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = pstate_latency_us; in dcn3_fpu_build_wm_range_table()
712 base->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2; in dcn3_fpu_build_wm_range_table()
713 base->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = 4; in dcn3_fpu_build_wm_range_table()
714 base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL; in dcn3_fpu_build_wm_range_table()
715 base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = 0; in dcn3_fpu_build_wm_range_table()
716 base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn3_fpu_build_wm_range_table()
717 base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn3_fpu_build_wm_range_table()
718 base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; in dcn3_fpu_build_wm_range_table()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| A D | dcn301_fpu.c | 245 .wm_inst = WM_D,
282 .wm_inst = WM_D,
429 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn301_fpu_calculate_wm_and_dlg()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 795 .wm_inst = WM_D,
832 .wm_inst = WM_D,
869 .wm_inst = WM_D,
906 .wm_inst = WM_D,
943 .wm_inst = WM_D,
980 .wm_inst = WM_D,
2295 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn21_calculate_wm()
2469 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY; in dcn21_clk_mgr_set_bw_params_wm_table()
2470 bw_params->wm_table.entries[WM_D].wm_inst = WM_D; in dcn21_clk_mgr_set_bw_params_wm_table()
2471 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING; in dcn21_clk_mgr_set_bw_params_wm_table()
[all …]
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | clk_mgr.h | 37 #define WM_D 3 macro
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| A D | dcn316_clk_mgr.c | 297 .wm_inst = WM_D,
334 .wm_inst = WM_D,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 257 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true; in dcn32_build_wm_range_table_fpu()
258 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_… in dcn32_build_wm_range_table_fpu()
259 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_… in dcn32_build_wm_range_table_fpu()
260 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2… in dcn32_build_wm_range_table_fpu()
261 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter… in dcn32_build_wm_range_table_fpu()
262 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL; in dcn32_build_wm_range_table_fpu()
263 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
264 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn32_build_wm_range_table_fpu()
265 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn32_build_wm_range_table_fpu()
266 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; in dcn32_build_wm_range_table_fpu()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| A D | dcn315_clk_mgr.c | 332 .wm_inst = WM_D,
369 .wm_inst = WM_D,
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| A D | dcn31_clk_mgr.c | 371 .wm_inst = WM_D,
408 .wm_inst = WM_D,
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| A D | dcn314_clk_mgr.c | 430 .wm_inst = WM_D,
467 .wm_inst = WM_D,
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| A D | dcn35_clk_mgr.c | 673 .wm_inst = WM_D,
710 .wm_inst = WM_D,
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| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 46 #define WM_D 3 macro
1423 ranges.reader_wm_sets[3].wm_inst = WM_D; in dcn_bw_notify_pplib_of_wm_ranges()
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