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Searched refs:WM_SET_COUNT (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr.h38 #define WM_SET_COUNT 4 macro
101 #define WM_SET_COUNT 4 macro
249 struct nv_wm_range_entry nv_entries[WM_SET_COUNT];
250 struct wm_range_table_entry entries[WM_SET_COUNT];
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
A Ddcn316_clk_mgr.c354 for (i = 0; i < WM_SET_COUNT; i++) { in dcn316_build_watermark_ranges()
552 for (i = 0; i < WM_SET_COUNT; i++) { in dcn316_clk_mgr_helper_populate_bw_params()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr.c460 for (i = 0; i < WM_SET_COUNT; i++) { in build_watermark_ranges()
678 for (i = 0; i < WM_SET_COUNT; i++) { in rn_clk_mgr_helper_populate_bw_params()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.c392 for (i = 0; i < WM_SET_COUNT; i++) { in vg_build_watermark_ranges()
603 for (i = 0; i < WM_SET_COUNT; i++) { in vg_clk_mgr_helper_populate_bw_params()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
A Ddcn315_clk_mgr.c389 for (i = 0; i < WM_SET_COUNT; i++) { in dcn315_build_watermark_ranges()
573 for (i = 0; i < WM_SET_COUNT; i++) { in dcn315_clk_mgr_helper_populate_bw_params()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_clk_mgr.c428 for (i = 0; i < WM_SET_COUNT; i++) { in dcn31_build_watermark_ranges()
620 for (i = 0; i < WM_SET_COUNT; i++) { in dcn31_clk_mgr_helper_populate_bw_params()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
A Ddcn314_clk_mgr.c492 for (i = 0; i < WM_SET_COUNT; i++) { in dcn314_build_watermark_ranges()
741 for (i = 0; i < WM_SET_COUNT; i++) { in dcn314_clk_mgr_helper_populate_bw_params()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr.c340 for (i = 0; i < WM_SET_COUNT; i++) in dcn3_notify_wm_ranges()
/drivers/gpu/drm/amd/display/dc/dml/calcs/
A Ddcn_calcs.c42 #define WM_SET_COUNT 4 macro
1390 ranges.num_reader_wm_sets = WM_SET_COUNT; in dcn_bw_notify_pplib_of_wm_ranges()
1391 ranges.num_writer_wm_sets = WM_SET_COUNT; in dcn_bw_notify_pplib_of_wm_ranges()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_clk_mgr.c753 for (i = 0; i < WM_SET_COUNT; i++) { in dcn35_build_watermark_ranges()
1060 for (i = 0; i < WM_SET_COUNT; i++) { in dcn35_clk_mgr_helper_populate_bw_params()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c2181 for (i = 0; i < WM_SET_COUNT; i++) { in patch_bounding_box()
2188 for (i = 0; i < WM_SET_COUNT; i++) { in patch_bounding_box()
2199 for (i = 0; i < WM_SET_COUNT; i++) { in patch_bounding_box()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr.c983 for (i = 0; i < WM_SET_COUNT; i++) in dcn32_notify_wm_ranges()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.c1316 for (i = 0; i < WM_SET_COUNT; i++) in dcn401_notify_wm_ranges()

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