| /drivers/ata/pata_parport/ |
| A D | bpck.c | 109 WR(4, 0); in bpck_write_block()
128 WR(4, 8); in bpck_write_block()
137 WR(4, 8); in bpck_write_block()
146 WR(4, 8); in bpck_write_block()
165 WR(4, 0); in bpck_read_block()
185 WR(4, 8); in bpck_read_block()
194 WR(4, 8); in bpck_read_block()
203 WR(4, 8); in bpck_read_block()
256 WR(5,8); in bpck_connect()
393 WR(4, 0); in bpck_read_eeprom()
[all …]
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| A D | epia.c | 114 WR(0x86, 8); in epia_connect()
167 WR(0x84, 3); in epia_read_block()
175 WR(0x84, 3); in epia_read_block()
183 WR(0x84, 3); in epia_read_block()
215 WR(0x84, 1); in epia_write_block()
220 WR(0x84, 0); in epia_write_block()
224 WR(0x84, 1); in epia_write_block()
229 WR(0x84, 0); in epia_write_block()
258 WR(2, 1); WR(3, 1); in epia_test_proto()
264 WR(0x84, 8); in epia_test_proto()
[all …]
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| A D | epat.c | 237 WR(0x8, 0x12); in epat_connect()
238 WR(0xc, 0x14); in epat_connect()
239 WR(0x12, 0x10); in epat_connect()
240 WR(0xe, 0xf); in epat_connect()
241 WR(0xf, 4); in epat_connect()
243 WR(0xe, 0xd); in epat_connect()
244 WR(0xf, 0); in epat_connect()
258 WR(8, 0x10); in epat_connect()
259 WR(0xc, 0x14); in epat_connect()
260 WR(0xa, 0x38); in epat_connect()
[all …]
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| /drivers/i2c/busses/ |
| A D | i2c-au1550.c | 107 WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC); in do_address()
123 WR(adap, PSC_SMBTXRX, addr); in do_address()
124 WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS); in do_address()
168 WR(adap, PSC_SMBTXRX, 0); in i2c_read()
196 WR(adap, PSC_SMBTXRX, data); in i2c_write()
205 WR(adap, PSC_SMBTXRX, data); in i2c_write()
258 WR(priv, PSC_SMBCFG, 0); in i2c_au1550_setup()
264 WR(priv, PSC_SMBCFG, cfg); in i2c_au1550_setup()
270 WR(priv, PSC_SMBCFG, cfg); in i2c_au1550_setup()
282 WR(priv, PSC_SMBCFG, cfg); in i2c_au1550_setup()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| A D | gddr3.c | 73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
79 WR = ram->next->bios.timing_10_WR; in nvkm_gddr3_calc()
87 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_gddr3_calc()
103 WR = ramxlat(ramgddr3_wr_lo, WR); in nvkm_gddr3_calc()
104 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0) in nvkm_gddr3_calc()
115 ram->mr[1] |= (WR & 0x03) << 4; in nvkm_gddr3_calc()
116 ram->mr[1] |= (WR & 0x04) << 5; in nvkm_gddr3_calc()
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| A D | sddr2.c | 63 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
68 WR = ram->next->bios.timing_10_WR; in nvkm_sddr2_calc()
74 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_sddr2_calc()
87 WR = ramxlat(ramddr2_wr, WR); in nvkm_sddr2_calc()
88 if (CL < 0 || WR < 0) in nvkm_sddr2_calc()
92 ram->mr[0] |= (WR & 0x07) << 9; in nvkm_sddr2_calc()
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| A D | sddr3.c | 72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
84 WR = ram->next->bios.timing_10_WR; in nvkm_sddr3_calc()
90 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_sddr3_calc()
102 WR = ramxlat(ramddr3_wr, WR); in nvkm_sddr3_calc()
103 if (CL < 0 || CWL < 0 || WR < 0) in nvkm_sddr3_calc()
107 ram->mr[0] |= (WR & 0x07) << 9; in nvkm_sddr3_calc()
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| A D | gddr5.c | 38 int WL, CL, WR, at[2], dt, ds; in nvkm_gddr5_calc() local
60 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; in nvkm_gddr5_calc()
70 if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35) in nvkm_gddr5_calc()
73 WR -= 4; in nvkm_gddr5_calc()
76 ram->mr[0] |= (WR & 0x0f) << 8; in nvkm_gddr5_calc()
118 ram->mr[8] |= (WR & 0x10) >> 3; in nvkm_gddr5_calc()
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| A D | ramnv50.c | 110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
176 T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL); in nv50_ram_timing_read()
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| A D | ramgt215.c | 375 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in gt215_ram_timing_calc()
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| /drivers/infiniband/ulp/rtrs/ |
| A D | README | 150 SEND_WITH_IMM WR, client When it recived new rkey message, it validates
193 SEND_WITH_IMM WR, client When it recived new rkey message, it validates
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