Searched refs:WREG32_RLC (Results 1 – 7 of 7) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_amdkfd_aldebaran.c | 155 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) + in kgd_gfx_aldebaran_set_address_watch()
159 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) + in kgd_gfx_aldebaran_set_address_watch()
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| A D | amdgpu_amdkfd_gfx_v12.c | 347 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) + in kgd_gfx_v12_set_address_watch()
351 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) + in kgd_gfx_v12_set_address_watch()
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| A D | amdgpu_amdkfd_gfx_v9.c | 854 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v9_set_address_watch()
858 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) + in kgd_gfx_v9_set_address_watch()
862 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_L) + in kgd_gfx_v9_set_address_watch()
872 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v9_set_address_watch()
886 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v9_clear_address_watch()
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| A D | amdgpu_amdkfd_gfx_v11.c | 772 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) + in kgd_gfx_v11_set_address_watch()
776 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) + in kgd_gfx_v11_set_address_watch()
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| A D | soc15_common.h | 110 #define WREG32_RLC(reg, value) \ macro
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| A D | soc15.c | 497 WREG32_RLC(reg, tmp); in soc15_program_register_sequence()
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| A D | gfx_v9_0.c | 2770 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), in gfx_v9_0_init_csb()
2772 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), in gfx_v9_0_init_csb()
2774 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), in gfx_v9_0_init_csb()
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