Searched refs:WREG32_SOC15_DPG_MODE (Results 1 – 7 of 7) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| A D | vcn_v4_0_5.c | 543 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode() 547 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode() 551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode() 555 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode() 557 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode() 561 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode() 564 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode() 567 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode() 569 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode() 574 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_5_mc_resume_dpg_mode() [all …]
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| A D | vcn_v4_0_3.c | 602 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode() 606 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode() 610 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode() 614 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode() 616 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode() 620 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode() 623 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode() 873 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF, in vcn_v4_0_3_start_dpg_mode() 2177 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_3_enable_ras() 2182 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_3_enable_ras() [all …]
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| A D | vcn_v2_5.c | 742 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode() 746 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode() 749 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode() 752 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode() 754 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode() 758 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode() 761 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode() 764 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode() 1016 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras() 1021 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras() [all …]
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| A D | vcn_v2_0.c | 512 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode() 516 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode() 519 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode() 522 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode() 524 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode() 528 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode() 531 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode() 534 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode() 536 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode() 541 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode() [all …]
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| A D | vcn_v4_0.c | 589 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode() 593 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode() 596 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode() 599 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode() 601 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode() 605 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode() 608 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode() 611 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode() 613 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode() 990 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_enable_ras() [all …]
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| A D | vcn_v3_0.c | 648 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode() 652 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode() 655 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode() 658 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode() 660 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode() 664 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode() 667 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode() 670 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode() 672 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode() 677 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode() [all …]
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| A D | amdgpu_vcn.h | 143 #define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \ macro
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