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Searched refs:WREG32_SOC15_IP (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dsdma_v7_0.c234 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, in sdma_v7_0_ring_set_wptr()
238 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, in sdma_v7_0_ring_set_wptr()
507 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); in sdma_v7_0_gfx_resume_instance()
582 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); in sdma_v7_0_gfx_resume_instance()
590 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); in sdma_v7_0_gfx_resume_instance()
597 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), temp); in sdma_v7_0_gfx_resume_instance()
720 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL), tmp); in sdma_v7_0_load_microcode()
722 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_LO), in sdma_v7_0_load_microcode()
724 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_HI), in sdma_v7_0_load_microcode()
729 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL), tmp); in sdma_v7_0_load_microcode()
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A Dsdma_v6_0.c232 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, in sdma_v6_0_ring_set_wptr()
235 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, in sdma_v6_0_ring_set_wptr()
468 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); in sdma_v6_0_enable()
515 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); in sdma_v6_0_gfx_resume_instance()
517 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); in sdma_v6_0_gfx_resume_instance()
586 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); in sdma_v6_0_gfx_resume_instance()
595 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); in sdma_v6_0_gfx_resume_instance()
602 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); in sdma_v6_0_gfx_resume_instance()
770 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); in sdma_v6_0_soft_reset()
774 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp); in sdma_v6_0_soft_reset()
[all …]
A Dsdma_v5_2.c479 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), in sdma_v5_2_ctx_switch_enable()
481 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), in sdma_v5_2_ctx_switch_enable()
483 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_2_ctx_switch_enable()
571 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); in sdma_v5_2_gfx_resume_instance()
572 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); in sdma_v5_2_gfx_resume_instance()
573 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_2_gfx_resume_instance()
574 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); in sdma_v5_2_gfx_resume_instance()
592 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), in sdma_v5_2_gfx_resume_instance()
594 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), in sdma_v5_2_gfx_resume_instance()
651 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); in sdma_v5_2_gfx_resume_instance()
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A Dsdma_v5_0.c398 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr()
401 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, in sdma_v5_0_ring_set_wptr()
635 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), in sdma_v5_0_ctx_switch_enable()
637 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), in sdma_v5_0_ctx_switch_enable()
639 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_0_ctx_switch_enable()
722 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); in sdma_v5_0_gfx_resume_instance()
723 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); in sdma_v5_0_gfx_resume_instance()
724 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_0_gfx_resume_instance()
725 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); in sdma_v5_0_gfx_resume_instance()
749 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), in sdma_v5_0_gfx_resume_instance()
[all …]
A Dsoc15_common.h86 #define WREG32_SOC15_IP(ip, reg, value) \ macro
A Dgfx_v12_0.c1894 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); in gfx_v12_0_enable_gui_idle_interrupt()
4731 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_gfx_eop_interrupt_state()
4739 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_gfx_eop_interrupt_state()
4782 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v12_0_set_compute_eop_interrupt_state()
4790 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v12_0_set_compute_eop_interrupt_state()
4900 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_priv_reg_fault_state()
4914 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_priv_reg_fault_state()
4946 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_bad_op_fault_state()
4960 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_bad_op_fault_state()
4991 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_priv_inst_fault_state()
A Dgfx_v11_0.c2212 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); in gfx_v11_0_enable_gui_idle_interrupt()
6322 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
6330 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
6379 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
6387 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
6497 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_priv_reg_fault_state()
6511 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_priv_reg_fault_state()
6543 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_bad_op_fault_state()
6557 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_bad_op_fault_state()
6697 WREG32_SOC15_IP(GC, target, tmp);
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A Damdgpu_gmc.c967 WREG32_SOC15_IP(GC, reg, tmp) : in amdgpu_gmc_set_vm_fault_masks()
968 WREG32_SOC15_IP(MMHUB, reg, tmp); in amdgpu_gmc_set_vm_fault_masks()
A Damdgpu_amdkfd_gfx_v10_3.c214 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); in hqd_load_v10_3()
A Dgmc_v9_0.c502 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
530 WREG32_SOC15_IP(MMHUB, reg, tmp); in gmc_v9_0_vm_fault_interrupt_state()
A Dgfx_v10_0.c5441 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); in gfx_v10_0_enable_gui_idle_interrupt()
9082 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
9088 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
9135 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
9141 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
9250 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_priv_reg_fault_state()
9264 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_priv_reg_fault_state()
9296 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_bad_op_fault_state()
9310 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_bad_op_fault_state()
9439 WREG32_SOC15_IP(GC, target, tmp); in gfx_v10_0_kiq_set_interrupt_state()
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A Damdgpu_amdkfd_gfx_v10.c228 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); in kgd_hqd_load()
A Dsoc15.c500 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); in soc15_program_register_sequence()
A Dgfx_v9_0.c5989 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
5995 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
6051 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v9_0_set_priv_reg_fault_state()
6087 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v9_0_set_bad_op_fault_state()

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