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Searched refs:WRITE_DATA_DST_SEL (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dvid.h142 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
A Dcikd.h266 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
A Dsoc15d.h130 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
A Dsid.h378 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
A Dnvd.h107 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
A Dgfx_v8_0.c892 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()
5121 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
5129 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
5137 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
5145 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
6231 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()
6240 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()
7136 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_ce_meta()
7169 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_de_meta()
A Dgfx_v7_0.c3186 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_wreg()
3971 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
3979 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
3987 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
3995 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
A Dgfx_v11_0.c515 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()
631 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v11_0_ring_test_ib()
5996 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()
6005 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()
6101 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v11_0_ring_emit_gfx_shadow()
6212 WRITE_DATA_DST_SEL(8) | in gfx_v11_0_ring_emit_de_meta()
A Dgfx_v9_0.c1165 WRITE_DATA_DST_SEL(0) | in gfx_v9_0_write_data_to_reg()
1248 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()
5649 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()
5658 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()
5687 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_ce_meta()
5785 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_de_meta()
A Dgfx_v9_4_3.c381 WRITE_DATA_DST_SEL(0) | in gfx_v9_4_3_write_data_to_reg()
475 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_4_3_ring_test_ib()
2974 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_4_3_ring_emit_fence_kiq()
2983 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_4_3_ring_emit_fence_kiq()
A Dgfx_v10_0.c4005 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()
4098 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v10_0_ring_test_ib()
8794 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()
8803 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()
8930 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_ce_meta()
8966 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_de_meta()
A Dgfx_v12_0.c525 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v12_0_ring_test_ib()
4533 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()
4542 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()
A Dgfx_v6_0.c2348 WRITE_DATA_DST_SEL(0))); in gfx_v6_0_ring_emit_wreg()
/drivers/gpu/drm/radeon/
A Dsid.h1637 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
A Dcik.c3742 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()
5684 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
5698 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
5705 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
5716 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
5727 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
A Dcikd.h1728 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
A Dsi.c5062 WRITE_DATA_DST_SEL(0))); in si_vm_flush()
5077 WRITE_DATA_DST_SEL(0))); in si_vm_flush()
5085 WRITE_DATA_DST_SEL(0))); in si_vm_flush()

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