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Searched refs:WR_CONFIRM (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
A Dvid.h151 #define WR_CONFIRM (1 << 20) macro
A Dcikd.h275 #define WR_CONFIRM (1 << 20) macro
A Dsoc15d.h139 #define WR_CONFIRM (1 << 20) macro
A Dsid.h387 #define WR_CONFIRM (1 << 20) macro
A Dnvd.h116 #define WR_CONFIRM (1 << 20) macro
A Dgfx_v9_4_3.c382 (wc ? WR_CONFIRM : 0)); in gfx_v9_4_3_write_data_to_reg()
475 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_4_3_ring_test_ib()
2974 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_4_3_ring_emit_fence_kiq()
2983 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_4_3_ring_emit_fence_kiq()
3018 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v9_4_3_ring_emit_wreg()
3024 cmd = WR_CONFIRM; in gfx_v9_4_3_ring_emit_wreg()
A Dgfx_v11_0.c515 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()
631 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v11_0_ring_test_ib()
5996 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()
6005 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()
6101 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v11_0_ring_emit_gfx_shadow()
6213 WR_CONFIRM) | in gfx_v11_0_ring_emit_de_meta()
6259 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v11_0_ring_emit_wreg()
6265 cmd = WR_CONFIRM; in gfx_v11_0_ring_emit_wreg()
A Dgfx_v9_0.c1166 (wc ? WR_CONFIRM : 0)); in gfx_v9_0_write_data_to_reg()
1248 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()
5649 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()
5658 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()
5688 WR_CONFIRM) | in gfx_v9_0_ring_emit_ce_meta()
5786 WR_CONFIRM) | in gfx_v9_0_ring_emit_de_meta()
5881 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v9_0_ring_emit_wreg()
5887 cmd = WR_CONFIRM; in gfx_v9_0_ring_emit_wreg()
A Dgfx_v8_0.c892 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()
6231 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()
6240 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()
6326 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v8_0_ring_emit_wreg()
6332 cmd = WR_CONFIRM; in gfx_v8_0_ring_emit_wreg()
7137 WR_CONFIRM) | in gfx_v8_0_ring_emit_ce_meta()
7170 WR_CONFIRM) | in gfx_v8_0_ring_emit_de_meta()
A Dgfx_v12_0.c525 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v12_0_ring_test_ib()
4533 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()
4542 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()
4671 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v12_0_ring_emit_wreg()
4677 cmd = WR_CONFIRM; in gfx_v12_0_ring_emit_wreg()
A Dgfx_v10_0.c4005 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()
4098 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v10_0_ring_test_ib()
8794 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()
8803 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()
8931 WR_CONFIRM) | in gfx_v10_0_ring_emit_ce_meta()
8967 WR_CONFIRM) | in gfx_v10_0_ring_emit_de_meta()
9013 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v10_0_ring_emit_wreg()
9019 cmd = WR_CONFIRM; in gfx_v10_0_ring_emit_wreg()
/drivers/gpu/drm/radeon/
A Dsid.h1646 #define WR_CONFIRM (1 << 20) macro
A Dcikd.h1737 #define WR_CONFIRM (1 << 20) macro

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