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/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/
A Drpcfn.h11 #ifndef X
12 # define X(UNIT, RPC, VAL) NV_VGPU_MSG_FUNCTION_##RPC = VAL, macro
16 X(RM, NOP, 0) enumerator
17 X(RM, SET_GUEST_SYSTEM_INFO, 1)
18 X(RM, ALLOC_ROOT, 2)
20 X(RM, ALLOC_MEMORY, 4)
21 X(RM, ALLOC_CTX_DMA, 5)
22 X(RM, ALLOC_CHANNEL_DMA, 6)
23 X(RM, MAP_MEMORY, 7)
25 X(RM, ALLOC_OBJECT, 9)
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/nvrm/
A Drpcfn.h11 #ifndef X
16 X(RM, NOP) // 0 enumerator
17 X(RM, SET_GUEST_SYSTEM_INFO) // 1
18 X(RM, ALLOC_ROOT) // 2
20 X(RM, ALLOC_MEMORY) // 4
21 X(RM, ALLOC_CTX_DMA) // 5
22 X(RM, ALLOC_CHANNEL_DMA) // 6
23 X(RM, MAP_MEMORY) // 7
25 X(RM, ALLOC_OBJECT) // 9
26 X(RM, FREE) //10
[all …]
/drivers/gpu/drm/nouveau/include/nvif/
A Dpush.h120 PUSH_DATA_(X, _pp, X##m, i0, i1, *_dd++, 1, "+0x%x", _i); \
187 PUSH_1(X, DATA_, 1, 0, o, (p), s, X##mA, (dA))
189 PUSH_2(X, DATA_, 1, 0, o, (p), s, X##mB, (dB), \
192 PUSH_3(X, DATA_, 1, 0, o, (p), s, X##mC, (dC), \
196 PUSH_4(X, DATA_, 1, 0, o, (p), s, X##mD, (dD), \
201 PUSH_5(X, DATA_, 1, 0, o, (p), s, X##mE, (dE), \
207 PUSH_6(X, DATA_, 1, 0, o, (p), s, X##mF, (dF), \
214 PUSH_7(X, DATA_, 1, 0, o, (p), s, X##mG, (dG), \
253 PUSH_1(X, DATAp, ds, 0, o, (p), s, X##mA, (dp))
255 PUSH_2(X, DATAp, ds, 0, o, (p), s, X##mB, (dp), \
[all …]
/drivers/staging/media/ipu3/
A Dipu3-tables.c9326 { 4, X, 1, 8, X, 8, X, 8, X }, /* bp_ctrl */
9331 1, 1, 1, X, X, 8, X, 7, X, 8, X, 8, X, 4, X
9421 .config = { 45, X, 0, X, 16, X, 45, X },
9423 .sharp = { { 50, X, 511, X, 50, X, 50, X },
9424 { 64, X, 0, X, 0, X},
9433 { 1, X, 2, X, 0, X, 0, X },
9451 .sense = { 8191, X, 0, X, 8191, X, 0, X },
9452 .gain = { 8, X, 0, X, 8, X, 0, X },
9453 .clip = { 8, X, 0, X, 8, X, 0, X },
9454 .frng = { 2, X, 200, X, 2, X, 1, 1, X },
[all …]
/drivers/gpu/drm/nouveau/include/nvhw/
A Ddrf.h66 #define NVVAL(A...) NVVAL_(X, ##A, NVVAL_I, NVVAL_N)(X, ##A)
71 #define NVDEF(A...) NVDEF_(X, ##A, NVDEF_I, NVDEF_N)(X, ##A)
130 #define DRF_RD(A...) DRF_RD_(X, ##A, DRF_RD_I, DRF_RD_N)(X, ##A)
137 #define DRF_WR(A...) DRF_WR_(X, ##A, DRF_WR_I, DRF_WR_N)(X, ##A)
148 #define DRF_MR(A...) DRF_MR_(X, ##A, DRF_MR_I, DRF_MR_N)(X, ##A)
155 #define DRF_RV(A...) DRF_RV_(X, ##A, DRF_RV_I, DRF_RV_N)(X, ##A)
163 #define DRF_WV(A...) DRF_WV_(X, ##A, DRF_WV_I, DRF_WV_N)(X, ##A)
171 #define DRF_WD(A...) DRF_WD_(X, ##A, DRF_WD_I, DRF_WD_N)(X, ##A)
181 #define DRF_MV(A...) DRF_MV_(X, ##A, DRF_MV_I, DRF_MV_N)(X, ##A)
191 #define DRF_MD(A...) DRF_MD_(X, ##A, DRF_MD_I, DRF_MD_N)(X, ##A)
[all …]
/drivers/gpu/drm/amd/pm/powerplay/inc/
A Dpp_endian.h27 #define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X) argument
28 #define PP_SMC_TO_HOST_UL(X) be32_to_cpu(X) argument
30 #define PP_HOST_TO_SMC_US(X) cpu_to_be16(X) argument
31 #define PP_SMC_TO_HOST_US(X) be16_to_cpu(X) argument
33 #define CONVERT_FROM_HOST_TO_SMC_UL(X) ((X) = PP_HOST_TO_SMC_UL(X)) argument
34 #define CONVERT_FROM_SMC_TO_HOST_UL(X) ((X) = PP_SMC_TO_HOST_UL(X)) argument
36 #define CONVERT_FROM_HOST_TO_SMC_US(X) ((X) = PP_HOST_TO_SMC_US(X)) argument
/drivers/staging/media/atomisp/pci/
A Dsh_css_param_dvs.h25 #define DVS_NUM_BLOCKS_X(X) round_up(DIV_ROUND_UP((X), DVS_BLOCKDIM_X), 2) argument
26 #define DVS_NUM_BLOCKS_X_CHROMA(X) DIV_ROUND_UP((X), DVS_BLOCKDIM_X) argument
30 #define DVS_NUM_BLOCKS_Y(X) DIV_ROUND_UP((X), DVS_BLOCKDIM_Y_LUMA) argument
31 #define DVS_NUM_BLOCKS_Y_CHROMA(X) DIV_ROUND_UP((X), DVS_BLOCKDIM_Y_CHROMA) argument
34 #define DVS_TABLE_IN_BLOCKDIM_X_LUMA(X) (DVS_NUM_BLOCKS_X(X) + 1) argument
35 #define DVS_TABLE_IN_BLOCKDIM_X_CHROMA(X) (DVS_NUM_BLOCKS_X_CHROMA(X) + 1) argument
36 #define DVS_TABLE_IN_BLOCKDIM_Y_LUMA(X) (DVS_NUM_BLOCKS_Y(X) + 1) argument
37 #define DVS_TABLE_IN_BLOCKDIM_Y_CHROMA(X) (DVS_NUM_BLOCKS_Y_CHROMA(X) + 1) argument
/drivers/gpu/drm/msm/disp/
A Dmdp_format.h67 #define MSM_FORMAT_IS_YUV(X) ((X)->flags & MSM_FORMAT_FLAG_YUV) argument
68 #define MSM_FORMAT_IS_DX(X) ((X)->flags & MSM_FORMAT_FLAG_DX) argument
69 #define MSM_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == MDP_FETCH_LINEAR) argument
70 #define MSM_FORMAT_IS_TILE(X) \ argument
71 (((X)->fetch_mode == MDP_FETCH_UBWC) && \
72 !((X)->flags & MSM_FORMAT_FLAG_COMPRESSED))
73 #define MSM_FORMAT_IS_UBWC(X) \ argument
74 (((X)->fetch_mode == MDP_FETCH_UBWC) && \
75 ((X)->flags & MSM_FORMAT_FLAG_COMPRESSED))
/drivers/media/dvb-frontends/
A Dstv0367_priv.h29 #define MAX(X, Y) ((X) >= (Y) ? (X) : (Y)) argument
30 #define MIN(X, Y) ((X) <= (Y) ? (X) : (Y)) argument
33 #define INRANGE(X, Y, Z) \ argument
34 ((((X) <= (Y)) && ((Y) <= (Z))) || \
35 (((Z) <= (Y)) && ((Y) <= (X))) ? 1 : 0)
38 #define MAKEWORD(X, Y) (((X) << 8) + (Y)) argument
41 #define LSB(X) (((X) & 0xff)) argument
A Dstv0900_priv.h17 #define INRANGE(X, Y, Z) ((((X) <= (Y)) && ((Y) <= (Z))) \ argument
18 || (((Z) <= (Y)) && ((Y) <= (X))) ? 1 : 0)
21 #define MAKEWORD(X, Y) (((X) << 8) + (Y)) argument
24 #define LSB(X) (((X) & 0xFF)) argument
/drivers/net/ethernet/freescale/
A Dfec.h315 #define FEC_R_DES_START(X) (((X) == 1) ? FEC_R_DES_START_1 : \ argument
318 #define FEC_X_DES_START(X) (((X) == 1) ? FEC_X_DES_START_1 : \ argument
321 #define FEC_R_BUFF_SIZE(X) (((X) == 1) ? FEC_R_BUFF_SIZE_1 : \ argument
325 #define FEC_DMA_CFG(X) (((X) == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1) argument
328 #define FEC_RCMR(X) (((X) == 2) ? FEC_RCMR_2 : FEC_RCMR_1) argument
332 #define IDLE_SLOPE(X) (((X) == 1) ? \ argument
341 #define RCMR_CMP(X) (((X) == 1) ? RCMR_CMP_1 : RCMR_CMP_2) argument
342 #define FEC_TX_BD_FTYPE(X) (((X) & 0xf) << 20) argument
387 #define FEC_ENET_RXF_GET(X) (((X) == 0) ? FEC_ENET_RXF_0 : \ argument
402 #define FEC_ITR_ICFT(X) (((X) & 0xff) << 20) argument
[all …]
/drivers/gpu/drm/imagination/
A Dpvr_params.c10 #define X(type_, name_, value_, desc_, ...) .name_ = (value_), macro
12 #undef X
26 #define X(type_, name_, value_, desc_, ...) \ macro
29 #undef X
102 #undef X
112 #define X(type_, name_, value_, desc_, mode_, update_) \ macro
115 #undef X
117 #define X(type_, name_, value_, desc_, mode_, update_) \ macro
127 #undef X
137 #define X(type_, name_, value_, desc_, mode_, update_) \ in pvr_params_debugfs_init() macro
[all …]
A Dpvr_params.h48 X(X32, fw_trace_mask, ROGUE_FWIF_LOG_TYPE_NONE, \
54 #define X(type_, name_, value_, desc_, ...) \ macro
57 #undef X
/drivers/net/ethernet/qlogic/qlcnic/
A Dqlcnic_dcb.c29 #define QLC_DCB_GET_TC_PRIO(X, P) ((X >> (P * 3)) & 0x7) argument
34 #define QLC_DCB_GET_PROTO_ID_APP(X) ((X >> 8) & 0xffff) argument
35 #define QLC_DCB_GET_SELECTOR_APP(X) (X & 0xff) argument
41 #define QLC_83XX_DCB_GET_NUMAPP(X) ((X >> 2) & 0xf) argument
42 #define QLC_83XX_DCB_TSA_VALID(X) (X & 0x1) argument
43 #define QLC_83XX_DCB_PFC_VALID(X) ((X >> 1) & 0x1) argument
44 #define QLC_83XX_DCB_GET_PRIOMAP_APP(X) (X >> 24) argument
46 #define QLC_82XX_DCB_GET_NUMAPP(X) ((X >> 12) & 0xf) argument
47 #define QLC_82XX_DCB_TSA_VALID(X) ((X >> 4) & 0x1) argument
48 #define QLC_82XX_DCB_PFC_VALID(X) ((X >> 5) & 0x1) argument
[all …]
/drivers/gpu/drm/xe/tests/
A Dxe_args_test.c12 #define foo X, Y, Z, Q in call_args_example()
26 #define foo X, Y, Z, Q in drop_first_arg_example()
37 int X = 1; in first_arg_example() local
39 #define foo X, Y, Z, Q in first_arg_example()
42 KUNIT_EXPECT_EQ(test, bar, X); in first_arg_example()
53 #define foo X, Y, Z, Q in last_arg_example()
67 #define foo X, Y, Z, Q in pick_arg_example()
83 #define foo(f) f(X) f(Y) f(Z) f(Q) in sep_comma_example()
102 #define FOO_ARGS X, Y, Z, Q
174 int X = -1; in first_arg_test() local
/drivers/net/ethernet/intel/
A De100.c430 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
434 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
437 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
440 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
441 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
443 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
449 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
454 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
456 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
459 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
[all …]
/drivers/hwmon/
A Dw83l786ng.c619 #define IN_UNIT_ATTRS(X) \ argument
621 &sda_in_min[X].dev_attr.attr, \
622 &sda_in_max[X].dev_attr.attr
624 #define FAN_UNIT_ATTRS(X) \ argument
627 &sda_fan_div[X].dev_attr.attr
629 #define TEMP_UNIT_ATTRS(X) \ argument
634 #define PWM_UNIT_ATTRS(X) \ argument
635 &sda_pwm[X].dev_attr.attr, \
637 &sda_pwm_enable[X].dev_attr.attr
639 #define TOLERANCE_UNIT_ATTRS(X) \ argument
[all …]
A Dpc87360.c597 #define VIN_UNIT_ATTRS(X) \ argument
598 &in_input[X].dev_attr.attr, \
599 &in_status[X].dev_attr.attr, \
600 &in_min[X].dev_attr.attr, \
601 &in_max[X].dev_attr.attr, \
603 &in_max_alarm[X].dev_attr.attr
861 #define THERM_UNIT_ATTRS(X) \ argument
1084 #define TEMP_UNIT_ATTRS(X) \ argument
1216 #define FAN_UNIT_ATTRS(X) \ argument
1219 &fan_div[X].dev_attr.attr, \
[all …]
/drivers/iio/pressure/
A Dt5403.c70 s32 S, O, X; in t5403_comp_pressure() local
93 X = (S * p_r + O) / 0x4000; in t5403_comp_pressure()
95 X += ((X - 75000) * (X - 75000) / 0x10000 - 9537) * in t5403_comp_pressure()
98 *val = X / 1000; in t5403_comp_pressure()
99 *val2 = (X % 1000) * 1000; in t5403_comp_pressure()
/drivers/char/agp/
A DKconfig19 Note that this is the only means to have X/GLX use
35 X on the following ALi chipsets. The supported chipsets
50 X on the ATI RadeonIGP family of chipsets.
57 X on AMD Irongate, 761, and 762 chipsets.
64 X using the on-CPU northbridge of the AMD Athlon64/Opteron CPUs.
74 This option gives you AGP support for the GLX component of X
86 X on NVIDIA chipsets including nForce and nForce2
93 X on Silicon Integrated Systems [SiS] chipsets.
110 X on VIA MVP3/Apollo Pro chipsets.
/drivers/staging/sm750fb/
A Dddk750_chip.c319 int N, M, X, d; in sm750_calc_pll_value() local
359 X = BIT(d); in sm750_calc_pll_value()
360 M = quo * X; in sm750_calc_pll_value()
361 M += fl_quo * X / 10000; in sm750_calc_pll_value()
363 M += (fl_quo * X % 10000) > 5000 ? 1 : 0; in sm750_calc_pll_value()
367 tmp_clock = pll->input_freq * M / N / X; in sm750_calc_pll_value()
/drivers/net/ethernet/intel/iavf/
A Diavf_adminq_cmd.h223 #define IAVF_CHECK_STRUCT_LEN(n, X) enum iavf_static_assert_enum_##X \ argument
224 { iavf_static_assert_##X = (n) / ((sizeof(struct X) == (n)) ? 1 : 0) }
229 #define IAVF_CHECK_CMD_LENGTH(X) IAVF_CHECK_STRUCT_LEN(16, X) argument
/drivers/iio/potentiometer/
A DKconfig84 tristate "Microchip MCP413X/414X/415X/416X/423X/424X/425X/426X Digital Potentiometer driver"
/drivers/iio/imu/
A Dadis16400.c794 ADIS16400_GYRO_CHAN(X, ADIS16400_XGYRO_OUT, 14),
797 ADIS16400_ACCEL_CHAN(X, ADIS16400_XACCL_OUT, 14),
800 ADIS16400_MAGN_CHAN(X, ADIS16400_XMAGN_OUT, 14),
809 ADIS16400_GYRO_CHAN(X, ADIS16400_XGYRO_OUT, 16),
812 ADIS16400_ACCEL_CHAN(X, ADIS16400_XACCL_OUT, 16),
820 ADIS16400_GYRO_CHAN(X, ADIS16400_XGYRO_OUT, 16),
826 ADIS16400_MAGN_CHAN(X, ADIS16400_XMAGN_OUT, 16),
849 ADIS16400_GYRO_CHAN(X, ADIS16400_XGYRO_OUT, 14),
855 ADIS16400_MAGN_CHAN(X, ADIS16400_XMAGN_OUT, 14),
867 ADIS16400_GYRO_CHAN(X, ADIS16400_XGYRO_OUT, 14),
[all …]
/drivers/gpu/drm/amd/display/dc/dio/dcn401/
A Ddcn401_dio_link_encoder.c40 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) argument
65 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) argument

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