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Searched refs:XEHP_DIS_BBL_SYSPIPE (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/xe/
A Dxe_wa.c404 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
453 XE_RTP_ACTIONS(SET(ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE))
/drivers/gpu/drm/xe/regs/
A Dxe_gt_regs.h483 #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11) macro
/drivers/gpu/drm/i915/gt/
A Dintel_gt_regs.h1132 #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11) macro
A Dintel_workarounds.c2846 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); in general_render_compute_wa_init()

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