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Searched refs:XELPDP_LANE_PCLK_PLL_ACK (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_cx0_phy_regs.h189 #define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4)) macro
A Dintel_cx0_phy.c3006 val |= XELPDP_LANE_PCLK_PLL_ACK(lane); in intel_cx0_get_pclk_pll_ack()

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