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Searched refs:XE_REG (Results 1 – 25 of 29) sorted by relevance

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/drivers/gpu/drm/xe/regs/
A Dxe_engine_regs.h46 #define ENGINE_ID(base) XE_REG((base) + 0x8c)
50 #define RING_TAIL(base) XE_REG((base) + 0x30)
53 #define RING_HEAD(base) XE_REG((base) + 0x34)
56 #define RING_START(base) XE_REG((base) + 0x38)
58 #define RING_CTL(base) XE_REG((base) + 0x3c)
73 #define RING_IPEHR(base) XE_REG((base) + 0x68)
75 #define RING_ACTHD(base) XE_REG((base) + 0x74)
86 #define RING_IMR(base) XE_REG((base) + 0xa8)
91 #define RING_EIR(base) XE_REG((base) + 0xb0)
92 #define RING_EMR(base) XE_REG((base) + 0xb4)
[all …]
A Dxe_gt_regs.h25 #define RPM_CONFIG0 XE_REG(0xd00)
37 #define GMD_ID XE_REG(0xd8c)
48 #define MCR_SELECTOR XE_REG(0xfdc)
88 #define CCS_AUX_INV XE_REG(0x4208)
124 #define FF_MODE2 XE_REG(0x6604)
242 #define GDRST XE_REG(0x941c)
246 #define MISCCPCTL XE_REG(0x9424)
320 #define RPNSWREQ XE_REG(0xa008)
331 #define RC_STATE XE_REG(0xa094)
348 #define CTC_MODE XE_REG(0xa26c)
[all …]
A Dxe_guc_regs.h16 #define DIST_DBS_POPULATED XE_REG(0xd08)
24 #define GTCR XE_REG(0x4274)
27 #define GUC_ARAT_C6DIS XE_REG(0xa178)
29 #define GUC_STATUS XE_REG(0xc000)
43 #define GUC_HEADER_INFO XE_REG(0xc014)
45 #define GUC_WOPCM_SIZE XE_REG(0xc050)
49 #define GUC_SHIM_CONTROL XE_REG(0xc064)
69 #define DMA_ADDR_0_LOW XE_REG(0xc300)
76 #define DMA_COPY_SIZE XE_REG(0xc310)
77 #define DMA_CTRL XE_REG(0xc314)
[all …]
A Dxe_oa_regs.h9 #define RPM_CONFIG1 XE_REG(0xd04)
12 #define EU_PERF_CNTL0 XE_REG(0xe458)
13 #define EU_PERF_CNTL4 XE_REG(0xe45c)
14 #define EU_PERF_CNTL1 XE_REG(0xe558)
15 #define EU_PERF_CNTL5 XE_REG(0xe55c)
16 #define EU_PERF_CNTL2 XE_REG(0xe658)
17 #define EU_PERF_CNTL6 XE_REG(0xe65c)
18 #define EU_PERF_CNTL3 XE_REG(0xe758)
20 #define OA_TLB_INV_CR XE_REG(0xceec)
23 #define OAR_OACONTROL XE_REG(0x2960)
[all …]
A Dxe_irq_regs.h14 #define DG1_MSTR_TILE_INTR XE_REG(0x190008)
18 #define GFX_MSTR_IRQ XE_REG(0x190010, XE_REG_OPTION_VF)
48 #define CRYPTO_RSVD_INTR_ENABLE XE_REG(0x190040)
68 #define HECI2_RSVD_INTR_MASK XE_REG(0x1900e4)
71 #define CRYPTO_RSVD_INTR_MASK XE_REG(0x1900f0)
73 #define CCS0_CCS1_INTR_MASK XE_REG(0x190100)
74 #define CCS2_CCS3_INTR_MASK XE_REG(0x190104)
75 #define XEHPC_BCS1_BCS2_INTR_MASK XE_REG(0x190110)
76 #define XEHPC_BCS3_BCS4_INTR_MASK XE_REG(0x190114)
77 #define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
[all …]
A Dxe_regs.h12 #define GU_CNTL_PROTECTED XE_REG(0x10100C)
15 #define GU_CNTL XE_REG(0x101010)
19 #define XEHP_CLOCK_GATE_DIS XE_REG(0x101014)
22 #define GU_DEBUG XE_REG(0x101018)
25 #define VIRTUAL_CTRL_REG XE_REG(0x10108c)
28 #define XEHP_MTCFG_ADDR XE_REG(0x101800)
31 #define GGC XE_REG(0x108040)
35 #define DSMBASE XE_REG(0x1080C0)
38 #define GSMBASE XE_REG(0x108100)
40 #define STOLEN_RESERVED XE_REG(0x1082c0)
[all …]
A Dxe_pcode_regs.h15 #define PVC_GT0_PACKAGE_ENERGY_STATUS XE_REG(0x281004)
16 #define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
17 #define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
18 #define PVC_GT0_PLATFORM_ENERGY_STATUS XE_REG(0x28106c)
19 #define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
21 #define BMG_FAN_1_SPEED XE_REG(0x138140)
22 #define BMG_FAN_2_SPEED XE_REG(0x138170)
23 #define BMG_FAN_3_SPEED XE_REG(0x1381a0)
24 #define BMG_VRAM_TEMPERATURE XE_REG(0x1382c0)
25 #define BMG_PACKAGE_TEMPERATURE XE_REG(0x138434)
A Dxe_gsc_regs.h23 #define HECI_H_CSR(base) XE_REG((base) + 0x4)
34 #define HECI_FWSTS1(base) XE_REG((base) + 0xc40)
39 #define HECI_FWSTS2(base) XE_REG((base) + 0xc48)
40 #define HECI_FWSTS3(base) XE_REG((base) + 0xc60)
41 #define HECI_FWSTS4(base) XE_REG((base) + 0xc64)
42 #define HECI_FWSTS5(base) XE_REG((base) + 0xc68)
44 #define HECI_FWSTS6(base) XE_REG((base) + 0xc6c)
46 #define HECI_H_GS1(base) XE_REG((base) + 0xc4c)
49 #define GSCI_TIMER_STATUS XE_REG(0x11ca28)
A Dxe_mchbar_regs.h21 #define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
30 #define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
35 #define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
37 #define PCU_CR_PACKAGE_TEMPERATURE XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5978)
40 #define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
A Dxe_i2c_regs.h14 #define REG_SG_REMAP_ADDR_PREFIX XE_REG(SOC_BASE + 0x0164)
15 #define REG_SG_REMAP_ADDR_POSTFIX XE_REG(SOC_BASE + 0x0168)
17 #define I2C_CONFIG_CMD XE_REG(I2C_CONFIG_SPACE_OFFSET + PCI_COMMAND)
18 #define I2C_CONFIG_PMCSR XE_REG(I2C_CONFIG_SPACE_OFFSET + 0x84)
A Dxe_pxp_regs.h14 #define KCR_INIT XE_REG(0x3860f0)
18 #define KCR_SIP XE_REG(0x386260)
21 #define KCR_GLOBAL_TERMINATE XE_REG(0x3860f8)
A Dxe_pmt.h13 #define PUNIT_TELEMETRY_GUID XE_REG(BMG_DISCOVERY_OFFSET + 0x4)
21 #define SG_REMAP_INDEX1 XE_REG(SOC_BASE + 0x08)
A Dxe_reg_defs.h120 #define XE_REG(r_, ...) ((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__)) macro
/drivers/gpu/drm/xe/compat-i915-headers/
A Dintel_uncore.h30 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_read()
38 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_read8()
46 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_read16()
73 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_posting_read()
81 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_write()
89 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_rmw()
98 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_wait_for_register()
109 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_wait_for_register_fw()
120 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in __intel_wait_for_register()
139 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_read_fw()
[all …]
/drivers/gpu/drm/xe/
A Dxe_pcode_api.h10 #define PCODE_MAILBOX XE_REG(0x138124)
25 #define PCODE_DATA0 XE_REG(0x138128)
26 #define PCODE_DATA1 XE_REG(0x13812C)
78 #define PCODE_SCRATCH(x) XE_REG(0x138320 + ((x) * 4))
92 #define BMG_PCIE_CAP XE_REG(0x138340)
A Dxe_pat.c169 struct xe_reg reg = XE_REG(_PAT_INDEX(i)); in program_pat()
175 xe_mmio_write32(&gt->mmio, XE_REG(_PAT_ATS), xe->pat.pat_ats->value); in program_pat()
177 xe_mmio_write32(&gt->mmio, XE_REG(_PAT_PTA), xe->pat.pat_pta->value); in program_pat()
210 u32 pat = xe_mmio_read32(&gt->mmio, XE_REG(_PAT_INDEX(i))); in xelp_dump()
299 pat = xe_mmio_read32(&gt->mmio, XE_REG(_PAT_INDEX(i))); in xelpg_dump()
336 pat = xe_mmio_read32(&gt->mmio, XE_REG(_PAT_INDEX(i))); in xe2_dump()
355 pat = xe_mmio_read32(&gt->mmio, XE_REG(_PAT_PTA)); in xe2_dump()
A Dxe_reg_whitelist.c20 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
51 XE_RTP_ACTIONS(WHITELIST(XE_REG(0x4400),
54 WHITELIST(XE_REG(0x4500),
A Dxe_i2c.c207 *val = xe_mmio_read32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET)); in xe_i2c_read()
216 xe_mmio_write32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET), val); in xe_i2c_write()
A Dxe_nvm.c46 return !(xe_mmio_read32(&gt->mmio, XE_REG(GEN12_CNTL_PROTECTED_NVM_REG)) & in xe_nvm_non_posted_erase()
A Dxe_irq.c32 #define IMR(offset) XE_REG(offset + 0x4)
33 #define IIR(offset) XE_REG(offset + 0x8)
34 #define IER(offset) XE_REG(offset + 0xc)
A Dxe_tuning.c18 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
A Dxe_guc_pc.c40 #define RP_STATE_CAP XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998)
45 #define FREQ_INFO_REC XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
49 #define GT_PERF_STATUS XE_REG(0x1381b4)
A Dxe_gt_mcr.c49 #define STEER_SEMAPHORE XE_REG(0xFD0)
/drivers/gpu/drm/xe/tests/
A Dxe_rtp_test.c23 #define REGULAR_REG1 XE_REG(1)
24 #define REGULAR_REG2 XE_REG(2)
25 #define REGULAR_REG3 XE_REG(3)
29 #define MASKED_REG1 XE_REG(1, XE_REG_OPTION_MASKED)
32 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
/drivers/gpu/drm/xe/display/
A Dxe_plane_initial.c32 struct xe_reg pipe_frmtmstmp = XE_REG(i915_mmio_reg_offset(PIPE_FRMTMSTMP(crtc->pipe))); in intel_plane_initial_vblank_wait()

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